Abstract: Apparatuses and techniques for handling faulty usage-based-disturbance data are described. In an example aspect, a memory device uses a report flag to indicate that an address of a row that corresponds to the faulty usage-based-disturbance data is logged at a global-bank level and is accessible by a host device. The report flag also enables the memory device to avoid reporting another error until the host device has cleared information associated with a previously-reported error. In another example aspect, the memory device temporarily prevents usage-based-disturbance mitigation from being performed based on the faulty usage-based-disturbance data. This means that if the faulty usage-based-disturbance data would otherwise trigger refreshing of one or more rows that are proximate to the row corresponding to the faulty usage-based-disturbance data, the memory device does not perform these refresh operations.

Abstract: Apparatuses and techniques for logging a memory address associated with faulty usage-based disturbance data are described. In an example aspect, a memory device can detect, at a local-bank level, a fault associated with usage-based disturbance data. This detection enables the memory device to log a row address associated with the faulty usage-based disturbance data. To avoid increasing a complexity and/or a size of the memory device, some implementations of the memory device can perform the address logging at the multi-bank level with the assistance of an engine, such as a test engine. The memory device stores the logged address in at least one mode register to communicate the fault to a memory controller. With the logged address, the memory controller can initiate a repair procedure to fix the faulty usage-based disturbance data.

Abstract: Single (1 T) and multi (MT) memory cell architectures may be included in a same memory array. In some embodiments, the individual memory cells of the MT memory cells may have a same polarity. In some embodiments, the individual memory cells of the MT memory cells may have complementary polarity. In some examples, digit lines at memory mats and edge memory mats may be folded for MT memory cells. In some examples, digit lines may be rerouted through local input-output line breaks for the MT memory cells. In some examples, the LIO lines from the MT memory cells may be twisted. In some examples, larger sense amplifiers may be used for the MT memory cells.

Abstract: Single (1T) and multi (MT) memory cell architectures may be included in a same memory array. In some embodiments, the individual memory cells of the MT memory cells may have a same polarity. In some embodiments, the individual memory cells of the MT memory cells may have complementary polarity. In some examples, digit lines at memory mats and edge memory mats may be folded for MT memory cells. In some examples, digit lines may be rerouted through local input-output line breaks for the MT memory cells. In some examples, the LIO lines from the MT memory cells may be twisted. In some examples, larger sense amplifiers may be used for the MT memory cells.

Abstract: Single (1T) and multi (MT) memory cell architectures may be included in a same memory array. In some embodiments, the individual memory cells of the MT memory cells may have a same polarity. In some embodiments, the individual memory cells of the MT memory cells may have complementary polarity. In some examples, digit lines at memory mats and edge memory mats may be folded for MT memory cells. In some examples, digit lines may be rerouted through local input-output line breaks for the MT memory cells. In some examples, the LIO lines from the MT memory cells may be twisted. In some examples, larger sense amplifiers may be used for the MT memory cells.

Abstract: Apparatuses and methods including memory commands for semiconductor memories are described. A controller provides a memory system with memory commands to access memory. The commands are decoded to provide internal signals and commands for performing operations, such as operations to access the memory array. The memory commands provided for accessing memory may include timing command and access commands. Examples of access commands include a read command and a write command. Timing commands may be used to control the timing of various operations, for example, for a corresponding access command. The timing commands may include opcodes that set various modes of operation during an associated access operation for an access command.

Abstract: An apparatus can include memory devices and a memory controller coupled to the memory devices via memory channels. The memory channels can disable a first memory channel associated with a first memory die in a respective memory chip of a memory device and perform a memory operation via a second memory channel involving a second memory die in the respective memory chip.

Abstract: This document describes apparatuses and techniques for an efficient command protocol for memory access. In various aspects, a memory controller may implement combined operations of different command types (e.g., an activation command plus a read, an activation command plus a write, or an activation command plus a pre-charge command) to better utilize a multiple clock ratio of a command bus (e.g., a (1.5+0.5) N operation in a dual clocking WCK2CK ratio of 4:1), which may improve utilization of a data bus for associated memory responses. By so doing, the efficient command protocol may improve power efficiency and system level performance of a computing system.

Abstract: Methods, systems, and devices for programmable column access are described. A device may transfer voltages from memory cells of a row in a memory array to respective digit lines for the memory cells. The voltages may be indicative of logic values stored at the memory cells. The device may communicate respective control signals to a set of multiplexers coupled with the digit lines, where each multiplexer is coupled with a respective subset of the digit lines. Each multiplexer may couple a digit line of the respective subset of digit lines with a respective sense component for that multiplexer based on the respective control signal for that multiplexer.

Abstract: Apparatuses and methods per-row count based refresh target identification. A memory device stores count values associated with the word lines. An aggressor detector circuit stores a maximum of the count values and a row address associated with the maximum count value. Responsive to a targeted refresh signal, the stored count value is compared to a threshold. If the count value has crossed the threshold, then a targeted refresh operation may be performed on one or more refresh addresses based on the stored address, and the count value may be reset.

Abstract: Described apparatuses and methods facilitate bus training with multiple dice, such as multiple memory dice. A controller can communicate with multiple dice over a bus to perform bus training by sending a test pattern and receiving in return a feedback pattern indicative of the bits detected by the dice. Because suitable signal timing can differ between dice, even those using the same bus, the controller may attempt to train each die separately from the others. In some situations, however, individualized training may be infeasible. To accommodate such situations, logic associated with two or more dice can combine the bits as detected from the test pattern into a combined feedback pattern. A timing parameter that is jointly suitable for multiple dice can be determined, and the bus training may be concluded, responsive to the combined feedback pattern matching the test pattern. The multiple dice may be stacked or linked.

Abstract: Described apparatuses and methods facilitate bus training with multiple dice, such as multiple memory dice. A controller can communicate with multiple dice to perform bus training by sending a test pattern and receiving in return a feedback pattern indicative of the bits detected by the dice. Because suitable signal timing can differ between dice, even those using the same bus, a controller may train each die separately from the others. In some situations, however, individualized training may be infeasible. To accommodate such situations, logic associated with two or more dice can combine, using at least one logical operation, bits as detected from the test pattern into a combined feedback pattern. A timing parameter that is jointly suitable for multiple dice can be determined, and the bus training may be concluded, responsive to the combined feedback pattern matching the test pattern. The multiple dice may be stacked or linked.

Abstract: Methods, systems, and devices for improved inter-memory movement in a multi-memory system are described. A memory device may receive from a host device a command to move data from a first memory controlled by a first controller to a second memory controller by a second controller. The memory device may use the first and second controllers to facilitate the movement of the data from the first memory to the second memory via a path external to the host device. The memory device may indicate to the host device when to suspend activity to the first memory or the second memory and when to resume activity to the first memory or second memory.

Abstract: Described apparatuses and methods relate to erroneous select die access (SDA) detection for a memory system. A memory system may include a memory controller and a memory device that are capable of implementing an SDA protocol that enables selective memory die access to multiple memory devices that couple to a command bus. A memory device can include logic that determines if signaling that conflicts with the SDA protocol is detected. If it is determined that conflicting signaling is detected, the logic may provide an indication of the conflicted signaling. In doing so, the erroneous SDA detection described herein may reduce the likelihood of a memory device erroneously masking memory dice, thereby limiting the memory device from exhibiting unexpected, and in some cases, dangerous behavior.

Abstract: Described apparatuses and methods relate to adaptive memory registers for a memory system that may support a nondeterministic protocol. To help manage power-delivery networks in a memory system, a device includes logic that can write values to memory registers associated with memory blocks of a memory array. The values indicate whether an associated memory block has been refreshed within a refresh interval. Other logic can read the registers to determine whether a block has been refreshed. The device also includes logic that can access data indicating a row address that was most recently, or is next to be, refreshed and write values representing the address to another register. The register can be read by other logic to determine whether a wordline potentially affected by an activation-based disturb event is near to being refreshed. These techniques can reduce the number of refresh operations performed, saving power and reducing costs.

Abstract: Described apparatuses and methods relate to self-refresh arbitration. In a memory system with multiple memory components, an arbiter is configured to manage the occurrence of self-refresh operations. In aspects, the arbiter can receive one or more self-refresh request signals from at least one memory controller for authorization to command one or more memory components to enter a self-refresh mode. Upon receiving the one or more self-refresh request signals, the arbiter, based on a predetermined configuration, can transmit one or more self-refresh enable signals to the at least one memory controller with authorization to command the one or more memory components to enter the self-refresh mode. The configuration can ensure that fewer than all memory components simultaneously enter the self-refresh mode. In so doing, memory components can perform self-refresh operations without exceeding an instantaneous power threshold. The arbiter can be included in, for instance, a Compute Express Link™ (CXL™) memory module.

Abstract: Apparatuses and methods for setting a duty cycler adjuster for improving clock duty cycle are disclosed. The duty cycle adjuster may be adjusted by different amounts, at least one smaller than another. Determining when to use the smaller adjustment may be based on duty cycle results. A duty cycle monitor may have an offset. A duty cycle code for the duty cycle adjuster may be set to an intermediate value of a duty cycle monitor offset. The duty cycle monitor offset may be determined by identifying duty cycle codes for an upper and for a lower boundary of the duty cycle monitor offset.

Abstract: Systems, apparatuses, and methods related to memory system refresh management are described herein. In an example, a refresh operation can be performed on a set of memory cells in a memory device. The memory device comprising a plurality of sets of memory cells corresponding to respective portions of an array of memory cells of the memory device. The refresh operation can include receiving a mode register write command. The refresh operation can include writing mode register data associated with the mode register write command. The refresh operation can be performed on the set of memory cells at an address location indicated by the written mode register data.

Abstract: Apparatuses and methods including memory commands for semiconductor memories are described. A controller provides a memory system with memory commands to access memory. The commands are decoded to provide internal signals and commands for performing operations, such as operations to access the memory array. The memory commands provided for accessing memory may include timing command and access commands. Examples of access commands include a read command and a write command. Timing commands may be used to control the timing of various operations, for example, for a corresponding access command. The timing commands may include opcodes that set various modes of operation during an associated access operation for an access command.

Abstract: Described apparatuses and methods provide configurable error correction code (ECC) circuitry and schemes that can utilize a shared ECC engine between multiple memory banks of a memory, including a low-power double data rate (LPDDR) memory. A memory device may include one or more dies with multiple memory banks. The configurable ECC circuitry can use an ECC engine that services a memory bank by producing ECC values based on data stored in the memory bank when data-masking functionality is enabled. When data-masking functionality is disabled, the configurable ECC circuitry can use the shared ECC engine that services at least two memory banks by producing ECC values with a larger quantity of bits based on respective data stored in the at least two memory banks. By using the shared ECC engine responsive to the data-masking functionality being disabled, the ECC functionality can provide higher data reliability with lower die area utilization.