Abstract: A semiconductor device that writes, into respective memory spaces of a plurality of separate memories constituting a search memory mat, an entry address corresponding to key data to be written. In this semiconductor device, pieces of divided data are assigned respectively to the separate memories, and, by employing each divided data as an address, entry addresses corresponding to the divided data are written sequentially into memory spaces specified by memory addresses of the separate memories (first writing process). In this first writing process, if another entry address is already written in an accessed memory space, no entry address is written into that memory space. If an entry address corresponding to a single one of the plurality of pieces of divided data is successfully written into a memory space, the first writing process is ended. Second write processing to a verification memory may also be performed. Key data may be written to a backup memory when a whole collision occurs.

Abstract: Disclosed is a semiconductor device that writes, into respective memory spaces of a plurality of divisional memories constituting a search memory mat, an entry address corresponding to key data to be written. In this semiconductor device, pieces of divisional data are assigned respectively to the divisional memories, and, by employing each divisional data as an address, an entry address corresponding to said divisional data is written sequentially into a memory space specified by a memory address of each said divisional memory (first writing process). In this first writing process, if another entry address is already written in an accessed memory space, no entry address is written into that memory space. If an entry address corresponding to one of the plurality of pieces of divisional data is successfully written into a memory space, the first writing process is ended.

Abstract: An arithmetic logic operation device including a memory device configured to store a lookup table and receive an input of a bit string N bits long, N being an integer of at least 2, the input bit string representing an address in the lookup table at which is stored multiple-bit data of which a part includes a bit representative of the result of a logical operation performed between the bits included in the input bit string. The memory device is accessed to output the bits included in the data stored at the address represented by the received bit string. The arithmetic logic device achieves arithmetic processing in a relatively short time on a relatively small circuit scale.

Abstract: An arithmetic logic operation device including a memory device configured to store a lookup table and receive an input of a bit string N bits long, N being an integer of at least 2, the input bit string representing an address in the lookup table at which is stored multiple-bit data of which a part includes a bit representative of the result of a logical operation performed between the bits included in the input bit string. The memory device is accessed to output the bits included in the data stored at the address represented by the received bit string. The arithmetic logic device achieves arithmetic processing in a relatively short time on a relatively small circuit scale.

Abstract: A multilayer wiring board includes an insulating layers stacked on one another, lands formed on an upper surface part of the multilayer wiring board, and a differential transmission line formed on or in each of the insulating layer. An electronic component is mounted on the lands. The differential transmission line is constituted of a pair of signal lines which extend from the lands toward a signal receiving end. Each of the signal lines is provided with an open stub which extends in a stacking direction of the insulating layers, and has a same width as a width of the signal lines, one end of the open stub being connected to a corresponding one of the signal lines, and another end of the open stub being open.

Abstract: The semiconductor device of the present invention includes a search memory mat having a configuration in which a location with which an entry address is registered is allocated in a y-axis direction, and key data is allocated in an x-axis direction and a control circuit connected to the search memory mat. In the search memory mat, a plurality of separate memories is formed such that a region to which the key data is allocated is separated into a plurality of regions along the y-axis direction. The control circuit includes an input unit to which the key data is input, a division unit which divides the key data input to the input unit into a plurality of pieces of key data, and a writing unit which allocates each piece of divided key data by the division unit into the separate memory using the divided key data as an address.

Abstract: The semiconductor device of the present invention includes a search memory mat having a configuration in which a location with which an entry address is registered is allocated in a y-axis direction, and key data is allocated in an x-axis direction and a control circuit connected to the search memory mat. In the search memory mat, a plurality of separate memories is formed such that a region to which the key data is allocated is separated into a plurality of regions along the y-axis direction. The control circuit includes an input unit to which the key data is input, a division unit which divides the key data input to the input unit into a plurality of pieces of key data, and a writing unit which allocates each piece of divided key data by the division unit into the separate memory using the divided key data as an address.

Abstract: According to an aspect of the invention, a semiconductor device includes a substrate having an opening area, a first semiconductor chip, and a second semiconductor chip. The first semiconductor chip has a first electrode for high-speed communication and that is disposed around the opening area on the substrate. The second semiconductor chip has a second electrode and third electrode for power and low-speed communication and that is disposed on the first semiconductor chip so that the first electrode is coupled with the second electrode by electrostatic coupling and dielectric coupling, the third electrode facing the opening area.

Abstract: A circuit substrate is presented. The circuit substrate comprises internal terminal electrode 2; a substrate 1; a wiring layer 21 formed on a portion of the surface of the substrate and having one end thereof connected to the internal terminal electrode; an insulating film contacting as a surface with the wiring layer; and an external terminal electrode 9 connected to the other end of the wiring layer and used for connecting to the exterior. The angle of the cross-section of the wiring layer taken perpendicularly to the surface of the substrate in the edge portion that the wiring layer contains is 55° (55 degree) or less, and the wiring layer that contains multiple mutually independent columnar crystals extending perpendicularly in a direction different from the direction of the surface of the substrate.

Abstract: A method of manufacturing a massive mixture of aluminum nitride and aluminum includes a first heat treatment process of manufacturing the massive mixture of aluminum nitride and aluminum by heating aluminum powder (21) and aluminum pieces (20) inserted into a vessel (13) at a temperature of a melting point of aluminum or higher under a nitrogen atmosphere. An oxide film is formed over the surface of the aluminum powder (21). The oxide film is, for example, a natural oxide film. The weight ratio of the aluminum powder (21) to the aluminum pieces (20) is, for example, 0.1 or less.

Abstract: In a memory/logic conjugate system, a plurality of cluster memory chips each including a plurality of cluster memories (20) including basic cells (10) arranged in a cluster, the basic cell including a memory circuit, and a controller chip that controls the plurality of cluster memories are three-dimensionally stacked, the plurality of cluster memories located along the stacking direction of the plurality of cluster memory chips and the controller chip are electrically coupled to the controller chip via a multibus (11) including a through-via, an arbitrary one of the basic cells is directly accessed through the multibus from the controller chip so that truth value data is written therein, and whereby the arbitrary basic cell is switched to a logic circuit as conjugate.

Abstract: A printed circuit board includes a ground layer, a power source layer, a signal wiring layer, an insulating layer and an electromagnetic radiation suppressing member. The power source layer is provided to be opposed to the ground layer. The signal wiring layer transmits a signal in a predetermined frequency domain. The insulating layer insulates the ground layer, the power source layer and the signal wiring layer from one another. The electromagnetic radiation suppressing member is provided to cover a circumferential edge of the insulating layer. The electromagnetic radiation suppressing member has a negative dielectric constant and a positive magnetic permeability in a frequency domain including the predetermined frequency domain.

Abstract: A method for manufacturing a wafer level package is provided that enables suppressing the wearing of a cutter and extending the lifetime of the cutter, including forming insulating first resin over the top face of a substrate, which includes a groove for wiring to be formed; forming a film of first metal that is to serve as a portion of the wiring on the top face of the first resin using physical vapor deposition; forming a film of second metal that is to form a portion of the wiring on the top face of the first metal, with a lower hardness than the first metal; setting a cutter at a height corresponding to a place where the film of the first metal is not formed on a side face of the groove or the film thickness is low; and cutting at least the first resin by scanning the cutter.

Abstract: A bandwidth bottleneck occurs because a crossbar switch is used to cope with an increase in scale. A memory/logic conjugate system according to the present invention, a plurality of cluster memory chips each including a plurality of cluster memories 20 including basic cells 10 arranged in a cluster, the basic cell 10 including a memory circuit, and a controller chip that controls the plurality of cluster memories are three-dimensionally stacked, the plurality of cluster memories 20 located along the stacking direction of the plurality of cluster memory chips and the controller chip are electrically coupled to the controller chip via a multibus 11 including a through-via, an arbitrary one of the basic cells 10 is directly accessed through the multibus 11 from the controller chip so that truth value data is written therein, and whereby the arbitrary basic cell 10 is switched to a logic circuit as conjugate.

Abstract: A circuit substrate is presented. The circuit substrate comprises internal terminal electrode 2; a substrate 1; a wiring layer 21 formed on a portion of the surface of the substrate and having one end thereof connected to the internal terminal electrode; an insulating film contacting as a surface with the wiring layer; and an external terminal electrode 9 connected to the other end of the wiring layer and used for connecting to the exterior. The angle of the cross-section of the wiring layer taken perpendicularly to the surface of the substrate in the edge portion that the wiring layer contains is 55° (55 degree) or less, and the wiring layer that contains multiple mutually independent columnar crystals extending perpendicularly in a direction different from the direction of the surface of the substrate.

Abstract: Disclosed is a semiconductor device wherein the switching speed of a transistor is increased. Specifically disclosed is a semiconductor device comprising a semiconductor layer formed on a part of an insulating layer, a first transistor formed on a lateral face of the semiconductor layer and having a first gate insulating film, a first gate electrode and two first impurity layers forming a source and a drain, and a second transistor formed on another lateral face of the semiconductor layer and having a second gate insulating film, a second gate electrode and two second impurity layers forming a source and a drain.

Abstract: There is a problem that a bandwidth bottleneck occurs because a crossbar switch is used to cope with an increase in scale. In an example of a memory/logic conjugate system according to the present invention, a plurality of cluster memory chips each including a plurality of cluster memories 20 including basic cells 10 arranged in a cluster, the basic cell 10 including a memory circuit, and a controller chip that controls the plurality of cluster memories are three-dimensionally stacked, the plurality of cluster memories 20 located along the stacking direction of the plurality of cluster memory chips and the controller chip are electrically coupled to the controller chip via a multibus 11 including a through-via, an arbitrary one of the basic cells 10 is directly accessed through the multibus 11 from the controller chip so that truth value data is written therein, and whereby the arbitrary basic cell 10 is switched to a logic circuit as conjugate.

Abstract: A signal transmission circuit includes a transmitting circuit for outputting a transmitting signal to a transmission line, a parallel circuit including a capacitor and a first resistance connected between an output terminal of the transmitting circuit and the transmission line, and a series circuit including an inductor and a second resistance connected between an output side of the parallel circuit and a ground.

Abstract: Disclosed is a paired low-characteristic impedance power line and ground line structure in which loop inductance is substantially 0. The paired low-characteristic impedance power line and ground line structure includes a laminated sheet in which a metal wiring layer having a power line and a ground line is provided on the surface of an insulating sheet, an insulating thin-film layer provided so as to cover the power line and the ground line, and a resistive layer provided on the surface of the insulating thin-film layer.

Abstract: A semiconductor integrated circuit package, a printed circuit board, a semiconductor apparatus, and a power supply wiring structure that allow attainment of stable power source and ground wiring without causing resonance even in a high-frequency bandwidth are provided. In an interior portion of the package, a power source wiring and a ground wiring constitute a pair wiring structure in which the power source wiring and the ground wiring are juxtaposed at a predetermined interval so as to establish electromagnetic coupling therebetween. A plurality of pair wiring structures are combined in such a manner that, when viewed in a section perpendicular to a wiring extending direction, the pair wiring assembly assumes a staggered (checkered) configuration. It is preferable that, each of the silicon chip and the printed circuit board, like the package, has pair wiring structures disposed inside.