Abstract: The disclosure provides a Sense Amplifier (SA), a memory and a method for controlling the SA, and relates to the technical field of semiconductor memories. The SA includes: an amplifier module; an offset voltage storage unit electrically connected to the amplifier module and configured to store an offset voltage of the amplifier module in an offset elimination stage of the SA; and a load compensation unit electrically connected to the amplifier module and configured to compensate a difference between loads of the amplifier module in an amplification stage of the SA. The disclosure may improve an accuracy of reading data of the SA.

Abstract: The sense amplifier includes: an amplification module configured to amplify a voltage transmitted by a bit line or a reference bit line, when the sense amplifier is at an amplification stage; a first switch module configured to control the amplification module to be disconnected from the reference bit line, when the sense amplifier performs a read operation for the bit line and is at the amplification stage. In the disclosure, the power consumption of the sense amplifier may be reduced.

Abstract: The present disclosure provides a sense amplifier, a memory, and a data readout method, and relates to the field of semiconductor memory technologies. The sense amplifier includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a first switch, a second switch, a third switch, and a fourth switch. During the offset compensation stage of the sense amplifier, the switching states of the first switch to the fourth switch are controlled so that the first NMOS transistor and the second NMOS transistor are configured to be in a cross-coupled amplification mode, and the first PMOS transistor and the second PMOS transistor are configured to be in a diode connection mode. The present disclosure enables to realize the offset compensation of the sense amplifier and improves the correctness of data readout by the memory.

Abstract: In an embodiment of the present invention, a clock generator circuit is disclosed to include a phase locked loop (PLL) that is responsive to a reference frequency and operative to generate a single clock frequency and a clock signal quadrature output frequency and a clock signal in-phase output with the frequency of the clock signal quadrature output frequency and the clock signal in-phase output frequency being a fraction of the frequency of the single clock frequency. The PLL includes a single voltage controlled oscillator (VCO) that generates the single clock frequency. A plurality of dividers is included in the clock generator circuit and is responsive to the clock signal quadrature output frequency and the clock signal in-phase output frequency and generates multiple clock frequencies, each clock frequency being a unique frequency, each of the plurality of dividers generating an output, the final output of the plurality of dividers being synchronized to the reference frequency.

Abstract: In an embodiment of the present invention, a clock generator circuit is disclosed to include a phase locked loop (PLL) that is responsive to a clock signal quadrature output frequency and a clock signal in-phase output frequency. The clock generator circuit generates a single clock frequency that is a fraction of the frequency of the clock signal quadrature output frequency and the clock signal in-phase output frequency. The PLL includes a single voltage controlled oscillator (VCO) that generates the single clock frequency. A plurality of dividers is included in the clock generator circuit and is responsive to the clock signal quadrature output frequency and the clock signal in-phase output frequency and generates multiple clock frequencies, each clock frequency being a unique frequency, each of the plurality of dividers generating an output that is phase and frequency synchronized to the single clock frequency.

Abstract: Fast settling circuits and methods designed to align input signal amplitude level and to remove DC offset voltages with minimal loss of low frequency signal in receiving analog circuits are disclosed. With the key innovative circuits and methods for signal peak alignment, the disclosed circuits and methods achieve fast settling without significant attenuation of the input signal. Peak aligning circuits and methods can be implemented along with conventional RC AC coupling circuits. In applying the aligning circuits and methods to differential signal pair, DC offsets can be easily removed.

Abstract: The present invention provides methods and apparatuses for a polyphase filter, comprising: a first and second cascoded differential amplifiers configured to receive a first and second differential signals, the first cascoded differential amplifier having a first resistor coupled between current legs of the first cascoded differential amplifier and the second cascoded differential amplifier having a first capacitor coupled between current legs of the second cascoded differential amplifier; and a third and fourth cascoded differential amplifiers configured to receive said first and said second differential signals, the third cascoded differential amplifier having a second resistor coupled between current legs of the third cascoded differential amplifier and the fourth cascoded differential amplifier having a second capacitor coupled between current legs of the fourth cascoded differential amplifier; wherein the first and second cascoded differential amplifiers are configured to provide a first differential outp

Abstract: Fast settling circuits and methods designed to align input signal amplitude level and to remove DC offset voltages with minimal loss of low frequency signal in receiving analog circuits are disclosed. With the key innovative circuits and methods for signal peak alignment, the disclosed circuits and methods achieve fast settling without significant attenuation of the input signal. Peak aligning circuits and methods can be implemented along with conventional RC AC coupling circuits. In applying the aligning circuits and methods to differential signal pair, DC offsets can be easily removed.

Abstract: A fast-setting DC offset removal circuit with continuous cutoff frequency switching is disclosed. In the preferred embodiment, the circuit is implemented using a pair of RC filters for receiving a differential signal pair and a continuous, variable resistance control circuit. The control circuit can be current-controlled or voltage controlled to provide fast settling of the received signal and the removal of the DC offset components. Additionally, by using a current-controlled control circuit, the cutoff frequency of the RC filter can be ramped from high to low in a continuous manner, thereby minimizing the generation of DC offsets.