Abstract: A method for manufacturing a semiconductor device includes forming a metal layer in a substrate and sequentially forming a barrier layer and an insulating layer on the substrate. The method includes performing a first etching step to form an opening in the insulating layer, and the opening does not expose the barrier layer. After the first etching step, a gap-filling layer is formed on the insulating layer and fills the opening. The method includes performing a second etching step to form a first via communicating with the opening in the gap-filling layer, and an upper portion of the opening is widened to form a trench. The method includes performing a third etching step to remove the gap-filling layer in a bottom of the opening and to deepen both the trench and the opening. The method includes forming a second via communicating with the opening to expose the metal layer.

Abstract: A pick-up structure of a memory device and a method of manufacturing the memory device are provided. The pick-up structure includes pick-up electrode stripes. Each pickup electrode stripe includes a main body portion in the peripheral pick-up region and an extending portion extending from the main body portion to the memory cell region. The extending portion is narrower than the main body portion. The sidewall surface of the extending portion is aligned with the sidewall surface of the main body portion.

Abstract: A processing apparatus for overlay shift includes a storage unit and a control unit, and is applicable to a semiconductor wafer with several inspection regions. Each of the inspection regions has several sets of overlay marks for inspection. One set of overlay marks includes an original alignment mark without any overlay shift, and several split alignment marks with predetermined overlay shifts arranged near the original alignment mark. The original after-etch inspection (AEI) overlay data of the inspection regions is stored in the storage unit. The after-develop inspection (ADI) overlay data of the original alignment mark and the split alignment marks are compared with the original AEI overlay data by the control unit, thereby acquiring ADI pre-bias data of the original alignment mark and the split alignment marks. The control unit determines whether an overlay shift compensation is performed according to the acquired ADI pre-bias data.

Abstract: A method for manufacturing a non-volatile memory device is provided. The method includes forming a trench through a sacrificial layer and extending into a substrate, filling a first insulating material into the trench, and implanting a dopant in the first insulating material by an implantation process. Then, the first insulating material is partially removed to form a first recess between the sacrificial layers. The lowest point of the first recess is lower than the top surface of the substrate. The method includes filling a second insulating material in the first recess and removing the sacrificial layer to form a second recess adjacent to the second insulating material. The method includes forming a first polycrystalline silicon layer in the second recess, and sequentially forming a dielectric layer and a second polycrystalline silicon layer on the first polycrystalline silicon layer.

Abstract: An image analysis method is provided. In the image analysis method, a to-be analyzed image is inputted into a region-based convolutional neural network (RCNN) model to obtain a masked image outputted from the RCNN. The center of a masked object in the masked image is calculated. The center is regarded as an origin of coordinate and the farthest coordinate point from the origin of coordinate in each of the four quadrants relative to the origin of coordinate are searched. The image analysis block is generated for each of the farthest coordinate points. The post-processing is performed on the image analysis blocks to obtain an object range.

Abstract: A manufacturing method for a semiconductor structure is provided. First active areas, a second active area, and a third active area are formed. A first dielectric layer is formed on the active areas. A patterned region that includes a cavity region and a dielectric region is formed in the first dielectric layer, and the cavity region surrounds the dielectric region. A filling layer is formed in the cavity region. Multiple first contact holes and at least one second contact hole that penetrate the first dielectric layer are formed. Each first contact hole exposes a portion of the corresponding first active area, and the second contact hole replaces the dielectric region and exposes a portion of the second active area. Metal layers are filled in to the first contact holes and the second contact hole.

Abstract: A method includes: forming a patterned dielectric layer, including a predetermined word line region and a predetermined pick-up neck region being separated by a first distance, and the patterned dielectric layer within the predetermined pick-up neck region has a second distance, wherein the first distance is smaller than or equal to the second distance; forming a spacer on sidewalls of the patterned dielectric layer; cutting off the spacer of a connecting portion of the predetermined word line region from the spacer of a remaining portion of the predetermined word line region; forming a mask pattern, including a first portion across the connecting portion and the predetermined pick-up neck region, wherein the spacer at the remaining portion is spaced apart from the first portion; and forming a dummy structure, word lines, and pick-up necks, wherein the dummy structure is located between the word lines and the pick-up necks.

Abstract: A method for manufacturing a non-volatile memory device is provided. The method includes forming a trench through a sacrificial layer and extending into a substrate, filling a first insulating material into the trench, and implanting a dopant in the first insulating material by an implantation process. Then, the first insulating material is partially removed to form a first recess between the sacrificial layers. The lowest point of the first recess is lower than the top surface of the substrate. The method includes filling a second insulating material in the first recess and removing the sacrificial layer to form a second recess adjacent to the second insulating material The method includes forming a first polycrystalline silicon layer in the second recess, and sequentially forming a dielectric layer and a second polycrystalline silicon layer on the first polycrystalline silicon layer.

Abstract: A method for manufacturing a semiconductor device includes forming a metal layer in a substrate and sequentially forming a barrier layer and an insulating layer on the substrate. The method includes performing a first etching step to form an opening in the insulating layer, and the opening does not expose the barrier layer. After the first etching step, a gap-filling layer is formed on the insulating layer and fills the opening. The method includes performing a second etching step to form a first via communicating with the opening in the gap-filling layer, and an upper portion of the opening is widened to form a trench. The method includes performing a third etching step to remove the gap-filling layer in a bottom of the opening and to deepen both the trench and the opening. The method includes forming a second via communicating with the opening to expose the metal layer.

Abstract: A method for forming a semiconductor memory structure includes sequentially forming an active layer, a hard mask layer and a core layer over a substrate, and etching the core layer to form a core pattern. The core pattern includes a first strip, a second strip, and a plurality of supporting features abutting the first and second strips. The method also includes forming a spacer layer alongside the core pattern, removing the core pattern, forming a photoresist pattern above the spacer layer, etching the hard mask layer using the photoresist pattern and the spacer layer to form a hard mask pattern, and transferring the hard mask pattern into the active layer to form a gate stack.

Abstract: An image analysis method includes: inputting a to-be analyzed image into a region-based convolutional neural network (RCNN) model; outputting a masked image; calculating the center of a masked object in the masked image using the region-based convolutional neural network model; calculating the center of a masked object in the masked image; regarding the center as a origin of coordinate, searching for the farthest coordinate point from the origin of coordinate in each of the four quadrants relative to the origin of coordinate; generating an image analysis block for each of the farthest coordinate points; and performing post-processing on the image analysis blocks to obtain an object range.

Abstract: A semiconductor device is provided and includes a first pad and a second pad, a first conductive connector and a second conductive connector, a first conductive structure and a second conductive structure. The first conductive connector and the second conductive connector are disposed over the first pad and the second pad. The first conductive structure is electrically connected to the first pad and the first conductive connector, and includes a first portion, a second portion and a connecting portion connecting the first and second portions. The first portion and the second portion are not overlapped in a vertical direction, and the first portion, the connecting portion and the second portion are integrally formed. The second conductive structure is electrically connected to the second pad and the second conductive connector, wherein a portion of the second conductive structure is overlapped with the first conductive structure therebeneath in the vertical direction.

Abstract: A semiconductor device is provided and includes a first pad and a second pad, a first conductive connector and a second conductive connector, a first conductive structure and a second conductive structure. The first conductive connector and the second conductive connector are disposed over the first pad and the second pad. The first conductive structure is electrically connected to the first pad and the first conductive connector, and includes a first portion, a second portion and a connecting portion connecting the first and second portions. The first portion and the second portion are not overlapped in a vertical direction, and the first portion, the connecting portion and the second portion are integrally formed. The second conductive structure is electrically connected to the second pad and the second conductive connector, wherein a portion of the second conductive structure is overlapped with the first conductive structure therebeneath in the vertical direction.

Abstract: A method of forming semiconductor devices includes providing a substrate with a patterned material layer formed thereon, forming a material layer on the patterned material layer, wherein the material layer has a first region with a lower top surface and a second region with a higher top surface, forming a flowable material layer on the material layer, wherein the flowable material layer exposes at least a portion of the second region of the material layer, removing the exposed portion of the second region of the material layer with the flowable material layer as a stop layer, removing the flowable material layer, and planarizing the material layer.

Abstract: A method of forming semiconductor devices includes providing a substrate with a patterned material layer formed thereon, forming a material layer on the patterned material layer, wherein the material layer has a first region with a lower top surface and a second region with a higher top surface, forming a flowable material layer on the material layer, wherein the flowable material layer exposes at least a portion of the second region of the material layer, removing the exposed portion of the second region of the material layer with the flowable material layer as a stop layer, removing the flowable material layer, and planarizing the material layer.

Abstract: Memory devices are provided. The memory device includes a substrate. A dielectric layer is disposed on the substrate and a plurality of resistive memory cells is disposed on the dielectric layer. Each resistive memory cell includes a via disposed in a first opening of the dielectric layer. A conductive layer is disposed on the via. The memory device further includes a capacitor structure including a bottom electrode, a variable resistance layer disposed on the bottom electrode and a top electrode disposed on the variable resistance layer, wherein the bottom electrode is disposed on the conductive layer.

Abstract: Memory devices are provided. The memory device includes a substrate. A dielectric layer is disposed on the substrate and a plurality of resistive memory cells is disposed on the dielectric layer. Each resistive memory cell includes a via disposed in a first opening of the dielectric layer. A conductive layer is disposed on the via. The memory device further includes a capacitor structure including a bottom electrode, a variable resistance layer disposed on the bottom electrode and a top electrode disposed on the variable resistance layer, wherein the bottom electrode is disposed on the conductive layer.

Abstract: An overlay mark applicable in a non-volatile memory includes two first X-direction isolation structures, two first Y-direction isolation structures, two second X-direction isolation structures, two second Y-direction isolation structures, a first dielectric layer, and a conductive layer. The first X-direction isolation structures, the first Y-direction isolation structures, the second X-direction isolation structures, and the second Y-direction isolation structures are disposed in a substrate. The first X-direction isolation structures and the first Y-direction isolation structures are arranged to a first rectangle, the second X-direction isolation structures and the second Y-direction isolation structures are arranged to a second rectangle, and the second rectangle is located in the first rectangle. The first dielectric layer is disposed on a surface of the substrate. The conductive layer is disposed on the first dielectric layer.

Abstract: An overlay mark applicable in a non-volatile memory includes two first X-direction isolation structures, two first Y-direction isolation structures, two second X-direction isolation structures, two second Y-direction isolation structures, a first dielectric layer, and a conductive layer. The first X-direction isolation structures, the first Y-direction isolation structures, the second X-direction isolation structures, and the second Y-direction isolation structures are disposed in a substrate. The first X-direction isolation structures and the first Y-direction isolation structures are arranged to a first rectangle, the second X-direction isolation structures and the second Y-direction isolation structures are arranged to a second rectangle, and the second rectangle is located in the first rectangle. The first dielectric layer is disposed on a surface of the substrate. The conductive layer is disposed on the first dielectric layer.

Abstract: A method of manufacturing an overlay mark is provided. Two first X-direction isolation structures, two first Y-direction isolation structures, two second X-direction isolation structures, and two second Y-direction isolation structures are formed in a substrate, where the first X-direction isolation structures and the first Y-direction isolation structures are arranged to a first rectangle, and the second X-direction isolation structures and the second Y-direction isolation structures are arranged to a second rectangle. The second rectangle is located in the first rectangle. A first dielectric layer and a conductive layer are formed sequentially on the substrate. A planarization process is performed to remove a portion of the conductive layer till the isolation structures are exposed. A second dielectric layer is formed on the substrate. A rectangle pattern is formed on the second dielectric layer. The sides of the rectangle pattern are located above the isolation structures.