Patents by Inventor Kaoru Saigoh

Kaoru Saigoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9059033
    Abstract: A semiconductor device is provided having a pad with an improved moisture blocking ability. The semiconductor device has: a circuit portion including a plurality of semiconductor elements formed on a semiconductor substrate; lamination of insulator covering the circuit portion, including a passivation film as an uppermost layer having openings; ferro-electric capacitors formed in the lamination of insulator; wiring structure formed in the lamination of insulator and connected to the semiconductor elements and the ferro-electric capacitors; pad electrodes connected to the wiring structure, formed in the lamination of insulator and exposed in the openings of the passivation film; a conductive pad protection film, including a Pd film, covering each pad electrode via the opening of the passivation film, and extending on the passivation film; and stud bump or bonding wire connected to the pad electrode via the conductive pad protection film.
    Type: Grant
    Filed: November 4, 2014
    Date of Patent: June 16, 2015
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Kaoru Saigoh, Kouichi Nagai
  • Publication number: 20150054129
    Abstract: A semiconductor device is provided having a pad with an improved moisture blocking ability. The semiconductor device has: a circuit portion including a plurality of semiconductor elements formed on a semiconductor substrate; lamination of insulator covering the circuit portion, including a passivation film as an uppermost layer having openings; ferro-electric capacitors formed in the lamination of insulator; wiring structure formed in the lamination of insulator and connected to the semiconductor elements and the ferro-electric capacitors; pad electrodes connected to the wiring structure, formed in the lamination of insulator and exposed in the openings of the passivation film; a conductive pad protection film, including a Pd film, covering each pad electrode via the opening of the passivation film, and extending on the passivation film; and stud bump or bonding wire connected to the pad electrode via the conductive pad protection film.
    Type: Application
    Filed: November 4, 2014
    Publication date: February 26, 2015
    Inventors: Kaoru Saigoh, Kouichi Nagai
  • Patent number: 8906705
    Abstract: A semiconductor device is provided having a pad with an improved moisture blocking ability. The semiconductor device has: a circuit portion including a plurality of semiconductor elements formed on a semiconductor substrate; lamination of insulator covering the circuit portion, including a passivation film as an uppermost layer having openings; ferro-electric capacitors formed in the lamination of insulator; wiring structure formed in the lamination of insulator and connected to the semiconductor elements and the ferro-electric capacitors; pad electrodes connected to the wiring structure, formed in the lamination of insulator and exposed in the openings of the passivation film; a conductive pad protection film, including a Pd film, covering each pad electrode via the opening of the passivation film, and extending on the passivation film; and stud bump or bonding wire connected to the pad electrode via the conductive pad protection film.
    Type: Grant
    Filed: November 10, 2011
    Date of Patent: December 9, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Kaoru Saigoh, Kouichi Nagai
  • Patent number: 8735945
    Abstract: A semiconductor device includes a transistor array including a plurality of transistors each having a gate electrode extended in a first direction, the plurality of transistors being arranged in a second direction intersecting the first direction, and a pad electrode arranged in the first direction of the transistor array and electrically connected to source regions of the plurality of transistors.
    Type: Grant
    Filed: September 2, 2011
    Date of Patent: May 27, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Masashi Shima, Kaoru Saigoh, Nobuhiro Misawa, Takao Sasaki
  • Patent number: 8507965
    Abstract: An insulation film (24) having a gradual inclination of a surface is formed by a high density plasma CVD method, an atmospheric pressure CVD method or the like, after a ferroelectric capacitor (23) is formed. Thereafter, an alumina film (25) is formed on the insulation film (24). According to the method, low coverage of the alumina film (25) does not become a problem, and the ferroelectric capacitor (23) is reliably protected.
    Type: Grant
    Filed: October 1, 2010
    Date of Patent: August 13, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Kazutoshi Izumi, Hitoshi Saito, Naoya Sashida, Kaoru Saigoh, Kouichi Nagai
  • Patent number: 8367541
    Abstract: After a ferroelectric capacitor is formed, an Al wiring (conductive pad) connected to the ferroelectric capacitor is formed. Then, a silicon oxide film and a silicon nitride film are formed around the Al wiring. Thereafter, as a penetration inhibiting film which inhibits penetration of moisture into the silicon oxide film, an Al2O3 film is formed.
    Type: Grant
    Filed: July 27, 2005
    Date of Patent: February 5, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Kouichi Nagai, Hitoshi Saito, Kaoru Sugawara, Makoto Takahashi, Masahito Kudo, Kazuhiro Asai, Yukimasa Miyazaki, Katsuhiro Sato, Kaoru Saigoh
  • Patent number: 8294241
    Abstract: A method of manufacturing a semiconductor device includes forming a wiring layer in a first insulating layer, forming a second insulating layer over the first insulating layer, forming a first conductive layer over the second insulating layer, forming a dielectric layer on the first conductive layer, forming a second conductive layer on the dielectric layer, selectively removing the second conductive layer to form an upper electrode on the dielectric layer, forming a first layer over the upper electrode and the dielectric layer, selectively removing the first layer, the dielectric layer, and the first conductive layer to form a lower electrode over which the dielectric layer and the first layer is entirely left, the upper electrode remaining partially over the lower electrode.
    Type: Grant
    Filed: April 29, 2011
    Date of Patent: October 23, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Tatsuro Osada, Kaoru Saigoh
  • Publication number: 20120132964
    Abstract: A semiconductor device includes a transistor array including a plurality of transistors each having a gate electrode extended in a first direction, the plurality of transistors being arranged in a second direction intersecting the first direction, and a pad electrode arranged in the first direction of the transistor array and electrically connected to source regions of the plurality of transistors.
    Type: Application
    Filed: September 2, 2011
    Publication date: May 31, 2012
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Masashi Shima, Kaoru Saigoh, Nobuhiro Misawa, Takao Sasaki
  • Publication number: 20120056322
    Abstract: A semiconductor device is provided having a pad with an improved moisture blocking ability. The semiconductor device has: a circuit portion including a plurality of semiconductor elements formed on a semiconductor substrate; lamination of insulator covering the circuit portion, including a passivation film as an uppermost layer having openings; ferro-electric capacitors formed in the lamination of insulator; wiring structure formed in the lamination of insulator and connected to the semiconductor elements and the ferro-electric capacitors; pad electrodes connected to the wiring structure, formed in the lamination of insulator and exposed in the openings of the passivation film; a conductive pad protection film, including a Pd film, covering each pad electrode via the opening of the passivation film, and extending on the passivation film; and stud bump or bonding wire connected to the pad electrode via the conductive pad protection film.
    Type: Application
    Filed: November 10, 2011
    Publication date: March 8, 2012
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Kaoru Saigoh, Kouichi Nagai
  • Patent number: 8076780
    Abstract: A semiconductor device is provided having a pad with an improved moisture blocking ability. The semiconductor device has: a circuit portion including a plurality of semiconductor elements formed on a semiconductor substrate; lamination of insulator covering the circuit portion, including a passivation film as an uppermost layer having openings; ferro-electric capacitors formed in the lamination of insulator; wiring structure formed in the lamination of insulator and connected to the semiconductor elements and the ferro-electric capacitors; pad electrodes connected to the wiring structure, formed in the lamination of insulator and exposed in the openings of the passivation film; a conductive pad protection film, including a Pd film, covering each pad electrode via the opening of the passivation film, and extending on the passivation film; and stud bump or bonding wire connected to the pad electrode via the conductive pad protection film.
    Type: Grant
    Filed: June 27, 2008
    Date of Patent: December 13, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Kaoru Saigoh, Kouichi Nagai
  • Publication number: 20110198724
    Abstract: A method of manufacturing a semiconductor device includes forming a wiring layer in a first insulating layer, forming a second insulating layer over the first insulating layer, forming a first conductive layer over the second insulating layer, forming a dielectric layer on the first conductive layer, forming a second conductive layer on the dielectric layer, selectively removing the second conductive layer to form an upper electrode on the dielectric layer, forming a first layer over the upper electrode and the dielectric layer, selectively removing the first layer, the dielectric layer, and the first conductive layer to form a lower electrode over which the dielectric layer and the first layer is entirely left, the upper electrode remaining partially over the lower electrode.
    Type: Application
    Filed: April 29, 2011
    Publication date: August 18, 2011
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Tatsuro OSADA, Kaoru SAIGOH
  • Patent number: 7982254
    Abstract: A protective film (56) having a water/hydrogen blocking function is formed so as to cover the periphery of a pad electrode (54a) while being electrically isolated from the pad electrode. A material selected in the embodiment for composing the protective film is a highly moisture-proof material having a water/hydrogen blocking function considerably superior to that of the insulating material, such as palladium (Pd) or palladium-containing material, and iridium (Ir) or iridium oxide (IrOx: typically x=2) or an iridium- or iridium oxide-containing material. An FeRAM capable of reliably preventing water/hydrogen from entering inside, and of maintaining high performance of the ferroelectric capacitor structure (30) may be realized only by a simple configuration.
    Type: Grant
    Filed: January 3, 2008
    Date of Patent: July 19, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Kouichi Nagai, Katsuhiro Sato, Kaoru Sugawara, Makoto Takahashi, Masahito Kudou, Kazuhiro Asai, Yukimasa Miyazaki, Kaoru Saigoh
  • Patent number: 7955944
    Abstract: A method of manufacturing a semiconductor device includes forming a wiring layer in a first insulating layer, forming a second insulating layer over the first insulating layer, forming a first conductive layer over the second insulating layer, forming a dielectric layer on the first conductive layer, forming a second conductive layer on the dielectric layer, selectively removing the second conductive layer to form an upper electrode on the dielectric layer, forming a first layer over the upper electrode and the dielectric layer, selectively removing the first layer, the dielectric layer, and the first conductive layer to form a lower electrode over which the dielectric layer and the first layer is entirely left, the upper electrode remaining partially over the lower electrode.
    Type: Grant
    Filed: April 15, 2009
    Date of Patent: June 7, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Tatsuro Osada, Kaoru Saigoh
  • Patent number: 7932579
    Abstract: A semiconductor device including a capacitor formed over a semiconductor substrate and including a lower electrode, a dielectric film formed over the lower electrode and an upper electrode formed over the dielectric film, an insulation film formed over the semiconductor substrate and the capacitor, and an electrode pad formed over the insulation film and including an alloy film of aluminum and magnesium.
    Type: Grant
    Filed: May 28, 2008
    Date of Patent: April 26, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Kouichi Nagai, Kaoru Saigoh
  • Patent number: 7915054
    Abstract: An ultra-thin semiconductor chip of an FeRAM, which is miniaturized and highly integrated with characteristic degradation of a ferroelectric capacitor suppressed though a thin package structure is applied to the FeRAM is realized. The semiconductor chip is molded up by using a sealing resin with a filler content set at a value in a range of 90 weight % to 93 weight % to produce a package structure.
    Type: Grant
    Filed: February 4, 2010
    Date of Patent: March 29, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Kaoru Saigoh, Kouichi Nagai
  • Publication number: 20110049675
    Abstract: A semiconductor device includes a capacitor provided above a substrate including electrodes and a ferroelectric film provided therebetween, a pad electrode electrically connected to one of the electrodes of the capacitor, the pad electrode being formed above the substrate, the pad electrode having a recess on a surface of the substrate, a protective film covering a part of the pad electrode other than the recess on the exposed surface, and a hydrogen absorbing film on the protective film and the recess of the pad electrode.
    Type: Application
    Filed: November 8, 2010
    Publication date: March 3, 2011
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventors: Kouichi NAGAI, Kaoru Saigoh
  • Publication number: 20110012230
    Abstract: An insulation film (24) having a gradual inclination of a surface is formed by a high density plasma CVD method, an atmospheric pressure CVD method or the like, after a ferroelectric capacitor (23) is formed. Thereafter, an alumina film (25) is formed on the insulation film (24). According to the method, low coverage of the alumina film (25) does not become a problem, and the ferroelectric capacitor (23) is reliably protected.
    Type: Application
    Filed: October 1, 2010
    Publication date: January 20, 2011
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Kazutoshi Izumi, Hitoshi Saito, Naoya Sashida, Kaoru Saigoh, Kouichi Nagai
  • Patent number: 7829476
    Abstract: A method of manufacturing a semiconductor device has forming a capacitor having electrodes and a ferroelectric film provided therebetween above a substrate, forming a pad electrode electrically connected to one of the electrodes of the capacitor above the substrate, forming a protective film covering the pad electrode over the substrate, forming an opening in the protective film exposing at least a part of the pad electrode, bringing a measurement terminal into contact with the exposed surface of the pad electrode, etching the surface of the pad electrode after the measurement terminal is brought into contact therewith, and forming a hydrogen absorbing film on the protective film and the pad electrode exposed through the opening.
    Type: Grant
    Filed: March 12, 2009
    Date of Patent: November 9, 2010
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Kouichi Nagai, Kaoru Saigoh
  • Publication number: 20100144064
    Abstract: An ultra-thin semiconductor chip of an FeRAM, which is miniaturized and highly integrated with characteristic degradation of a ferroelectric capacitor suppressed though a thin package structure is applied to the FeRAM is realized. The semiconductor chip is molded up by using a sealing resin with a filler content set at a value in a range of 90 weight % to 93 weight % to produce a package structure.
    Type: Application
    Filed: February 4, 2010
    Publication date: June 10, 2010
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventors: Kaoru Saigoh, Kouichi Nagai
  • Patent number: 7683412
    Abstract: An ultra-thin semiconductor chip of an FeRAM, which is miniaturized and highly integrated with characteristic degradation of a ferroelectric capacitor suppressed though a thin package structure is applied to the FeRAM is realized. The semiconductor chip is molded up by using a sealing resin with a filler content set at a value in a range of 90 weight % to 93 weight % to produce a package structure.
    Type: Grant
    Filed: February 28, 2006
    Date of Patent: March 23, 2010
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Kaoru Saigoh, Kouichi Nagai