Abstract: There is provided an overcurrent protection circuit having a sense transistor through which a first sense current proportional to an output current of an output transistor flows, a voltage-current converting circuit connected between an input terminal of the output transistor and an output terminal thereof, and configured to output a first current, a first current-voltage converting circuit configured to output a first voltage proportional to the first current, a voltage detection circuit configured to detect the first voltage and to output a second sense current based on the output current of the output transistor, a second current-voltage converting circuit through which the first sense current and the second sense current flow, and a current limiting circuit configured to limit the output current of the output transistor based on a second voltage supplied from the second current-voltage converting circuit.

Abstract: A voltage regulator includes an error amplifier, and the error amplifier includes a differential pair constituted by a pair of transistors, a current adjustment circuit that provides a bias current proportional to an output current supplied from an output transistor to the differential pair, a source output circuit and a sink output circuit that provide a current based on a current flowing through the differential pair to an output terminal of the error amplifier, and a phase compensation circuit that controls a current of the sink output circuit based on a current of the current adjustment circuit.

Abstract: A voltage regulator includes an error amplifier which receives a feedback voltage and a reference voltage, an amplifier circuit which receives an output voltage of the error amplifier and controls a gate of an output transistor by a first output voltage, and a non-regulation detection circuit which detects a non-regulation state of the voltage regulator based on a second output voltage of the amplifier circuit. The amplifier circuit includes a first transistor receiving the output voltage of the error amplifier at a gate of the first transistor, and a second transistor connected to a drain of the first transistor, and provides the second output voltage based on a gate-source voltage of the second transistor.

Abstract: A voltage regulator includes an error amplifier which receives a feedback voltage and a reference voltage and thereby controls a gate voltage of an output transistor, a non-regulation detection circuit having a differential amplifier circuit operating on a current corresponding to an output current of the output transistor, and an overshoot suppression circuit having an overshoot detection circuit which enables an overshoot detection by a signal indicating the detection of non-regulation state from the non-regulation detection circuit.

Abstract: A voltage regulator includes an error amplifier, and the error amplifier includes a differential pair constituted by a pair of transistors, a current adjustment circuit that provides a bias current proportional to an output current supplied from an output transistor to the differential pair, a source output circuit and a sink output circuit that provide a current based on a current flowing through the differential pair to an output terminal of the error amplifier, and a phase compensation circuit that controls a current of the sink output circuit based on a current of the current adjustment circuit.

Abstract: Between a power supply potential and a reference potential, a first PMOS transistor and a first NMOS transistor are connected in series via an inverting output node and a second PMOS transistor and a second NMOS transistor are connected in series via a non-inverting output node. A third NMOS transistor is connected in parallel to the first NMOS transistor and a fourth NMOS transistor is connected in parallel to the second NMOS transistor. A gate of the first PMOS transistor and a gate of the third NMOS transistor are connected to the non-inverting output node and a gate of the second PMOS transistor and a gate of the fourth NMOS transistor are connected to the inverting output node. The first and second NMOS transistors receive a non-inverted signal and an inverted signal of an input signal at their gates, respectively.

Abstract: A reference voltage circuit includes: a depletion type MOS transistor and an enhancement type MOS transistor connected in series, and having gates thereof connected in common, the enhancement type MOS transistor providing a reference voltage from a drain thereof, the depletion type MOS transistor including at least a first depletion type MOS transistor and a second depletion type MOS transistor connected in series; and a capacitor having one end connected to a drain of the first depletion type MOS transistor, and the other end connected to a source of the first depletion type MOS transistor.

Abstract: A reference voltage circuit includes: a depletion type MOS transistor and an enhancement type MOS transistor connected in series, and having gates thereof connected in common, the enhancement type MOS transistor providing a reference voltage from a drain thereof, the depletion type MOS transistor including at least a first depletion type MOS transistor and a second depletion type MOS transistor connected in series; and a capacitor having one end connected to a drain of the first depletion type MOS transistor, and the other end connected to a source of the first depletion type MOS transistor.

Abstract: To provide a voltage regulator capable of switching a voltage of an output terminal from an internal voltage to an external voltage while suppressing an increase in circuit scale. The voltage regulator includes a voltage output circuit configured to generate a constant internal voltage lower than an external voltage applied to an input terminal from the external voltage and supplying the constant internal voltage to an output terminal, a temperature sensing circuit configured to decrease an output voltage of an output node thereof according to a rise in temperature, an overheat detection circuit connected to the output node of the temperature sensing circuit and a test terminal, and a voltage detection circuit connected to the output node of the temperature sensing circuit and the test terminal.

Abstract: To provide a voltage regulator capable of switching a voltage of an output terminal from an internal voltage to an external voltage while suppressing an increase in circuit scale. The voltage regulator includes a voltage output circuit configured to generate a constant internal voltage lower than an external voltage applied to an input terminal from the external voltage and supplying the constant internal voltage to an output terminal, a temperature sensing circuit configured to decrease an output voltage of an output node thereof according to a rise in temperature, an overheat detection circuit connected to the output node of the temperature sensing circuit and a test terminal, and a voltage detection circuit connected to the output node of the temperature sensing circuit and the test terminal.

Abstract: Provided is a monitoring circuit for a system including an LDO regulator. The monitoring circuit includes: a non-saturation detection circuit configured to detect a non-saturation state of an output transistor of the LDO regulator configured to supply a power supply voltage to an MPU; a current detection circuit configured to detect that an output current from the output transistor is equal to or more than a predetermined current value; and a watchdog timer configured to monitor operation of the MPU. The watchdog timer is enabled when the output transistor is not in a non-saturation state and an output current from the output transistor is equal to or more than a predetermined current value.

Abstract: There is provided an overcurrent protection circuit having a sense transistor through which a first sense current proportional to an output current of an output transistor flows, a voltage-current converting circuit connected between an input terminal of the output transistor and an output terminal thereof, and configured to output a first current, a first current-voltage converting circuit configured to output a first voltage proportional to the first current, a voltage detection circuit configured to detect the first voltage and to output a second sense current based on the output current of the output transistor, a second current-voltage converting circuit through which the first sense current and the second sense current flow, and a current limiting circuit configured to limit the output current of the output transistor based on a second voltage supplied from the second current-voltage converting circuit.

Abstract: Provided is a monitoring circuit equipped with a first abnormality detection circuit which detects a first abnormal state of a semiconductor device under surveillance, a second abnormality detection circuit which detects a second abnormal state of the semiconductor device under surveillance, a reset circuit which outputs a reset signal based on a logical sum of a first abnormality detection signal output from the first abnormality detection circuit and a second abnormality detection signal output from the second abnormality detection circuit to a first output terminal, and an output holding circuit which stores which of the first abnormality detection signal and the second abnormality detection signal is supplied, and outputs an abnormality discrimination signal corresponding thereto to a second output terminal.

Abstract: Between a power supply potential and a reference potential, a first PMOS transistor and a first NMOS transistor are connected in series via an inverting output node and a second PMOS transistor and a second NMOS transistor are connected in series via a non-inverting output node. A third NMOS transistor is connected in parallel to the first NMOS transistor and a fourth NMOS transistor is connected in parallel to the second NMOS transistor. A gate of the first PMOS transistor and a gate of the third NMOS transistor are connected to the non-inverting output node and a gate of the second PMOS transistor and a gate of the fourth NMOS transistor are connected to the inverting output node. The first and second NMOS transistors receive a non-inverted signal and an inverted signal of an input signal at their gates, respectively.

Abstract: Provided is a semiconductor device including a MOS analog circuit which has a high reliability and a low manufacturing cost, and in which latent failure is easily detected. The MOS analog circuit is switched to a test state or an operating state based on a control signal that is externally supplied. In the test state, a voltage between a power supply terminal and a reference terminal is applied to a gate oxide film of a MOS transistor included in the MOS analog circuit.

Abstract: Provided is an overheat detection circuit having a small circuit scale, low cost, and low electric power consumption. The overheat detection circuit implemented in a CMOS semiconductor device includes: a reference voltage circuit connected between a base and an emitter of a parasitic bipolar transistor; and a current detection circuit connected to the emitter of the parasitic bipolar transistor, in which the current detection circuit is configured to detect a flow of a current through the parasitic bipolar transistor to output an overheat detection signal.

Abstract: Provided is a voltage regulator which is not affected by a variation in output impedance of a reference voltage circuit, that is, which is configured to output voltage with a small change due to temperature. Two reference voltages respectively having positive and negative temperature coefficients are added together through transconductance amplifiers having large input impedances, respectively, and the resultant is amplified.

Abstract: To provide a low-pass filter circuit which is high in noise elimination capability and starts its output stably and at high speed, and a power supply device. A low-pass filter circuit is provided which is equipped with a capacitance element connected to an output terminal, and a resistance circuit connected between an input terminal and the output terminal, and in which the resistance circuit is equipped with a first MOS transistor connected between the input terminal and the output terminal, and an amplifier which has a first input terminal to which the input terminal is connected, a second input terminal to which the output terminal is connected, and an output terminal to which a gate of the first MOS transistor is connected, and which controls a time constant of the low-pass filter circuit.

Abstract: Provided is a semiconductor device including a MOS analog circuit which has a high reliability and a low manufacturing cost, and in which latent failure is easily detected. The MOS analog circuit is switched to a test state or an operating state based on a control signal that is externally supplied. In the test state, a voltage between a power supply terminal and a reference terminal is applied to a gate oxide film of a MOS transistor included in the MOS analog circuit.

Abstract: Provided is a voltage regulator which is not affected by a variation in output impedance of a reference voltage circuit, that is, which is configured to output voltage with a small change due to temperature. Two reference voltages respectively having positive and negative temperature coefficients are added together through transconductance amplifiers having large input impedances, respectively, and the resultant is amplified.