Patents by Inventor Kaoru Tokushige
Kaoru Tokushige has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20010009532Abstract: A semiconductor memory device comprises a memory cell group comprising a plurality of memory cells arranged in matrix; a specification circuit for specifying sequentially memory cells addressed by consecutive addresses in the memory cells, and for enterring them in an active state; a data input/output (I/O) circuit for performing a data read-out/write-in operation (data I/O operation) for the consecutive memory cells specified by the specification circuit under a control based on a read-out/write-in signal provided from an external section; a counter circuit for counting the number of cycles of a basic clock signal provided from an external section; and a controller for receiving at least one or more specification signals provided from an external section, for outputting a control signal per specification signal for specifying a particular cycle as a starting cycle to count the number of the cycles of the basic clock signal, and for instructing the counter circuit to count the number of counts of the basic clType: ApplicationFiled: March 21, 2001Publication date: July 26, 2001Inventors: Haruki Toda, Shozo Saito, Kaoru Tokushige
-
Patent number: 6249481Abstract: A semiconductor memory device comprises a memory cell group comprising a plurality of memory cells arranged in matrix; a specification circuit for specifying sequentially memory cells addressed by consecutive addresses in the memory cells, and for enterring them in an active state; a data input/output (I/O) circuit for performing a data read-out/write-in operation (data I/O operation) for the consecutive memory cells specified by the specification circuit under a control based on a read-out/write-in signal provided from an external section; a counter circuit for counting the number of cycles of a basic clock signal provided from an external section; and a controller for receiving at least one or more specification signals provided from an external section, for outputting a control signal per specification signal for specifying a particular cycle as a starting cycle to count the number of the cycles of the basic clock signal, and for instructing the counter circuit to count the number of counts of the basic clType: GrantFiled: November 4, 1999Date of Patent: June 19, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Haruki Toda, Shozo Saito, Kaoru Tokushige
-
Patent number: 6172911Abstract: The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite operation, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.Type: GrantFiled: April 1, 1999Date of Patent: January 9, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Tomoharu Tanaka, Masaki Momodomi, Hideo Kato, Hiroto Nakai, Yoshiyuki Tanaka, Riichiro Shirota, Seiichi Aritome, Yasuo Itoh, Yoshihisa Iwata, Hiroshi Nakamura, Hideko Odaira, Yutaka Okamoto, Masamichi Asano, Kaoru Tokushige
-
Patent number: 6097666Abstract: A block size buffer and block address pre-decoder are provided for a flash memory. At the time of data erase, the size of a block to be erased is input to the block size buffer and a set of block addresses is input to the block address pre-decoder. An output signal of the block size buffer is supplied to and decoded by the block address pre-decoder, a row decoder is controlled based on the result of pre-decoding, and a plurality of addressing including the above block address as a top address are selected in a multiple manner. Then, a plurality of successive blocks are simultaneously selected to simultaneously erase data in the memory cells in the plurality of blocks.Type: GrantFiled: November 6, 1998Date of Patent: August 1, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Koji Sakui, Kaoru Tokushige, Kenichi Imamiya
-
Patent number: 6028794Abstract: A nonvolatile semiconductor memory device comprises a plurality of nonvolatile memory cells, which can be electrically programmed and erased, the plurality of nonvolatile memory cells divided into a plurality of blocks, a block erase circuit for erasing the plurality of nonvolatile memory cells contained in the plurality of blocks at the same time per block, erase operation times storage section for storing the number of erase operations of the nonvolatile memory cells to be erased at the same time by the block erase circuit per block in a number of erase operation storage region, and read time setting section for setting the read time based on the number of the erase operations stored in the number of erase operation storage region at the time of reading the storage data in the nonvolatile memory cells.Type: GrantFiled: January 15, 1998Date of Patent: February 22, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Hiroto Nakai, Kaoru Tokushige
-
Patent number: 5995442Abstract: A semiconductor memory device comprises a memory cell group comprising a plurality of memory cells arranged in matrix; a specification circuit for specifying sequentially memory cells addressed by consecutive addresses in the memory cells, and for entering them in an active state; a data input/output (I/O) circuit for performing a data read-out/write-in operation (data I/O operation) for the consecutive memory cells specified by the specification circuit under a control based on a read-out/write-in signal provided from an external section; a counter circuit for counting the number of cycles of a basic clock signal provided from an external section; and a controller for receiving at least one or more specification signals provided from an external section, for outputting a control signal per specification signal for specifying a particular cycle as a starting cycle to count the number of the cycles of the basic clock signal, and for instructing the counter circuit to count the number of counts of the basic cloType: GrantFiled: January 25, 1999Date of Patent: November 30, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Haruki Toda, Shozo Saito, Kaoru Tokushige
-
Patent number: 5926436Abstract: A semiconductor memory device comprises a memory cell group comprising a plurality of memory cells arranged in matrix; a specification circuit for specifying sequentially memory cells addressed by consecutive addresses in the memory cells, and for entering them in an active state; a data input/output (I/O) circuit for performing a data read-out/write-in operation (data I/O operation) for the consecutive memory cells specified by the specification circuit under a control based on a read-out/write-in signal provided from an external section; a counter circuit for counting the number of cycles of a basic clock signal provided from an external section; and a controller for receiving at least one or more specification signals provided from an external section, for outputting a control signal per specification signal for specifying a particular cycle as a starting cycle to count the number of the cycles of the basic clock signal, and for instructing the counter circuit to count the number of counts of the basic cloType: GrantFiled: February 3, 1998Date of Patent: July 20, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Haruki Toda, Shozo Saito, Kaoru Tokushige
-
Patent number: 5909399Abstract: The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite oepration, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.Type: GrantFiled: June 19, 1998Date of Patent: June 1, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Tomoharu Tanaka, Masaki Momodomi, Hideo Kato, Hiroto Nakai, Yoshiyuki Tanaka, Riichiro Shirota, Seiichi Aritome, Yasuo Itoh, Yoshihisa Iwata, Hiroshi Nakamura, Hideko Odaira, Yutaka Okamoto, Masamichi Asano, Kaoru Tokushige
-
Patent number: 5875486Abstract: A semiconductor memory device comprises a memory cell group comprising a plurality of memory cells arranged in matrix; a specification circuit for specifying sequentially memory cells addressed by consecutive addresses in the memory cells, and for enterring them in an active state; a data input/output (I/O) circuit for performing a data read-out/write-in operation (data I/O operation) for the consecutive memory cells specified by the specification circuit under a control based on a read-out/write-in signal provided from an external section; a counter circuit for counting the number of cycles of a basic clock signal provided from an external section; and a controller for receiving at least one or more specification signals provided from an external section, for outputting a control signal per specification signal for specifying a particular cycle as a starting cycle to count the number of the cycles of the basic clock signal, and for instructing the counter circuit to count the number of counts of the basic clType: GrantFiled: August 15, 1997Date of Patent: February 23, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Haruki Toda, Shozo Saito, Kaoru Tokushige
-
Patent number: 5818791Abstract: The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite operation, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.Type: GrantFiled: March 27, 1997Date of Patent: October 6, 1998Assignee: Kabushiki Kaisha ToshibaInventors: Tomoharu Tanaka, Masaki Momodomi, Hideo Kato, Hiroto Nakai, Yoshiyuki Tanaka, Riichiro Shirota, Seiichi Aritome, Yasuo Itoh, Yoshihisa Iwata, Hiroshi Nakamura, Hideko Odaira, Yutaka Okamoto, Masamichi Asano, Kaoru Tokushige
-
Patent number: 5793696Abstract: The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite oepration, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.Type: GrantFiled: April 8, 1997Date of Patent: August 11, 1998Assignee: Kabushiki Kaisha ToshibaInventors: Tomoharu Tanaka, Masaki Momodomi, Hideo Kato, Hiroto Nakai, Yoshiyuki Tanaka, Riichiro Shirota, Seiichi Aritome, Yasuo Itoh, Yoshihisa Iwata, Hiroshi Nakamura, Hideko Odaira, Yutaka Okamoto, Masamichi Asano, Kaoru Tokushige
-
Patent number: 5777925Abstract: A semiconductor non-volatile memory device, e.g., flash type E2 PROM capable of electrically carrying out block erasing is provided. This semiconductor device comprises a column decoder supplied with a column address signal to select a bit line, a row decoder supplied with a row address signal to select a word line, at least one NOR type memory cell array, and at least one NAND type memory cell array. In this semiconductor device, the NOR type memory cell array and the NAND type memory cell array are connected to common bit lines, and are connected to different word lines. Thus, both the NOR type and NAND type memory cell arrays are disposed on the same chip to realize one chip configuration so that improvement in the mounting area can be attained.Type: GrantFiled: July 3, 1997Date of Patent: July 7, 1998Assignee: Kabushiki Kaisha ToshibaInventor: Kaoru Tokushige
-
Patent number: 5740122Abstract: A semiconductor memory device comprises a memory cell group comprising a plurality of memory cells arranged in matrix: a specification circuit for specifying sequentially memory cells addressed by consecutive addresses in the memory cells, and for enterring them in an active state; a data input/output (I/O) circuit for performing a data read-out/write-in operation (data I/O operation) for the consecutive memory cells specified by the specification circuit under a control based on a read-out/write-in signal provided from an external section; a counter circuit for counting the number of cycles of a basic clock signal provided from an external section; and a controller for receiving at least one or more specification signals provided from an external section, for outputting a control signal per specification signal for specifying a particular cycle as a starting cycle to count the number of the cycles of the basic clock signal, and for instructing the counter circuit to count the number of counts of the basic clType: GrantFiled: January 7, 1997Date of Patent: April 14, 1998Assignee: Kabushiki Kaisha ToshibaInventors: Haruki Toda, Shozo Saito, Kaoru Tokushige
-
Patent number: 5737637Abstract: A semiconductor memory device comprises a memory cell group comprising a plurality of memory cells arranged in matrix; a specification circuit for specifying sequentially memory cells addressed by consecutive addresses in the memory cells, and for setting them in an active state; a data input/output (I/O) circuit for performing a data read-out/write-in operation (data I/O operation) for the consecutive memory cells specified by the specification circuit under a control based on a read-out/write-in signal provided from an external section; a counter circuit for counting the number of cycles of a basic clock signal provided from an external section; and a controller for receiving at least one or more specification signals provided from an external section, for outputting a control signal per specification signal for specifying a particular cycle as a starting cycle to count the number of the cycles of the basic clock signal, and for instructing the counter circuit to count the number of counts of the basic clocType: GrantFiled: September 27, 1996Date of Patent: April 7, 1998Assignee: Kabushiki Kaisha ToshibaInventors: Haruki Toda, Shozo Saito, Kaoru Tokushige
-
Patent number: 5724300Abstract: The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite operation, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.Type: GrantFiled: January 16, 1997Date of Patent: March 3, 1998Assignee: Kabushiki Kaisha ToshibaInventors: Tomoharu Tanaka, Masaki Momodomi, Hideo Kato, Hiroto Nakai, Yoshiyuki Tanaka, Riichiro Shirota, Seiichi Aritome, Yasuo Itoh, Yoshihisa Iwata, Hiroshi Nakamura, Hideko Odaira, Yutaka Okamoto, Masamichi Asano, Kaoru Tokushige
-
Patent number: 5615165Abstract: The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite operation, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.Type: GrantFiled: December 21, 1995Date of Patent: March 25, 1997Assignee: Kabushiki Kaisha ToshibaInventors: Tomoharu Tanaka, Masaki Momodomi, Hideo Kato, Hiroto Nakai, Yoshiyuki Tanaka, Riichiro Shirota, Seiichi Aritome, Yasuo Itoh, Yoshihisa Iwata, Hiroshi Nakamura, Hideko Odaira, Yutaka Okamoto, Masamichi Asano, Kaoru Tokushige
-
Patent number: 5612925Abstract: A semiconductor memory device, including a memory cell array having a plurality of memory cells arranged in rows and columns, the memory cells storing data and being selected according to address signals. The device includes a control unit which receives a clock signal and a first control, or trigger, signal for outputting a plurality of the data in synchronism with the clock signal after the first control signal is asserted. The output of the data beginning after a number of clock cycles (N) of the clock signal (N being a positive integer .gtoreq.2) after the first control signal is asserted, a different one of the data being output at each of the clock cycles after the output begins until the plurality of data is output.Type: GrantFiled: June 5, 1995Date of Patent: March 18, 1997Assignee: Kabushiki Kaisha ToshibaInventors: Haruki Toda, Shozo Saito, Kaoru Tokushige
-
Patent number: 5587963Abstract: A semiconductor memory device includes a memory cell having a plurality of memory cells arranged in rows and columns, the memory cells storing data and being selected according to address signals. The device also includes a control unit to receive a clock signal and a first control, or trigger, signal for outputting a plurality of the data in synchronism with the clock signal after the first control signal is asserted. The output of the data begins a number of clock cycles (N) of the clock signal (N being a positive integer.gtoreq.2) after the first control signal is asserted, a different one of the data being output at each of the clock cycles after the output begins until the plurality of data is output.Type: GrantFiled: April 24, 1995Date of Patent: December 24, 1996Assignee: Kabushiki Kaisha ToshibaInventors: Haruki Toda, Shozo Saito, Kaoru Tokushige
-
Patent number: 5546351Abstract: The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite operation, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.Type: GrantFiled: October 20, 1994Date of Patent: August 13, 1996Assignee: Kabushiki Kaisha ToshibaInventors: Tomoharu Tanaka, Masaki Momodomi, Hideo Kato, Hiroto Nakai, Yoshiyuki Tanaka, Riichiro Shirota, Seiichi Aritome, Yasuo Itoh, Yoshihisa Iwata, Hiroshi Nakamura, Hideko Odaira, Yutaka Okamoto, Masamichi Asano, Kaoru Tokushige
-
Patent number: 5500829Abstract: A semiconductor memory device including a memory cell group comprising a plurality of memory cells arranged in a matrix; a specification circuit for specifying a plurality of memory cells addressed by sequential addresses in the memory cells, and for entering them in an active state; a data input/output (I/O) circuit for performing a data read-out/write-in operation (data I/O operation) for the memory cells specified by the specification circuit under a control based on a read-out/write-in signal provided from an external section; a counter circuit for counting the number in response to cycles of a basic clock signal provided from an external section; and a controller for receiving at least one or more specification signals provided from an external section, for outputting a control signal per specification signal for specifying a particular cycle as a starting cycle to count the number of the cycles in response to the basic clock signal, and for instructing the counter circuit to count the number of cycles iType: GrantFiled: April 5, 1994Date of Patent: March 19, 1996Assignee: Kabushiki Kaisha ToshibaInventors: Haruki Toda, Shozo Saito, Kaoru Tokushige