Patents by Inventor Karel Ptacek
Karel Ptacek has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240097555Abstract: A driver is suitable for use with a gallium nitride (GaN) power stage, and includes a voltage regulator and a high side driver. The voltage regulator provides a boot voltage between first and second terminals thereof that varies within a range between a turn-on voltage of a GaN transistor, and a safe voltage limit between a gate and a source thereof throughout an active time of said GaN transistor. The high side driver has an input for receiving a high side drive signal, an output for coupling to said gate of said GaN transistor, a power supply terminal coupled to said first terminal of said voltage regulator, and a ground terminal for coupled to said second terminal of said voltage regulator.Type: ApplicationFiled: September 21, 2022Publication date: March 21, 2024Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Karel PTACEK, Dhruv CHOPRA
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Patent number: 11817784Abstract: Switching circuits, half-bridge power converters, and methods for operating a switching circuit including a switching transistor coupled to a load. The method includes applying, with a driver, a gate voltage to the switching transistor. The method also includes generating, with a feedback capacitor, a feedback current based on a change in a voltage sensed at a drain terminal of the switching transistor when the switching transistor turns on. The method further includes applying the feedback current to the driver to limit the gate voltage applied to the switching transistor. The method also includes adjusting, with a controller, a switching slew rate of the switching transistor by draining an amount of the feedback current.Type: GrantFiled: January 11, 2022Date of Patent: November 14, 2023Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Karel Ptacek, Roman Stuler, Roman Radvan
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Publication number: 20230223850Abstract: Switching circuits, half-bridge power converters, and methods for operating a switching circuit including a switching transistor coupled to a load. The method includes applying, with a driver, a gate voltage to the switching transistor. The method also includes generating, with a feedback capacitor, a feedback current based on a change in a voltage sensed at a drain terminal of the switching transistor when the switching transistor turns on. The method further includes applying the feedback current to the driver to limit the gate voltage applied to the switching transistor. The method also includes adjusting, with a controller, a switching slew rate of the switching transistor by draining an amount of the feedback current.Type: ApplicationFiled: January 11, 2022Publication date: July 13, 2023Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Karel PTACEK, Roman STULER, Roman RADVAN
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Patent number: 11018216Abstract: In accordance with an embodiment, an electrical element includes a first portion of a first dielectric material between a first portion of a first electrical conductor and a first portion of a second electrical conductor and a second portion of the first dielectric material between a second portion of the first electrical conductor and a first portion of a third electrical conductor. In accordance with another embodiment, an electrical component has a plurality of dopant regions formed in a semiconductor material, where the dopant regions include a plurality of dopant regions formed in a dopant region of the same conductivity type. A plurality of dopant regions of an opposite conductivity type are formed in corresponding dopant regions of the first conductivity type. A metallization system is formed over the semiconductor material, where a portion of the metallization system contacts the semiconductor material.Type: GrantFiled: June 24, 2019Date of Patent: May 25, 2021Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Richard Scott Burton, Karel Ptacek
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Patent number: 10812066Abstract: A pull-down circuit includes a control circuit generating an activation signal in response to a supply voltage, a first reference voltage, and a feedback signal, and a charge pump configured to generate a control signal in response to the activation signal and control a switching device using the control signal. The switching device is a field-effect transistor (FET) and is coupled to a power switch and pulls down a voltage level of a gate of the power switch to prevent a premature turn-on of the power switch.Type: GrantFiled: March 7, 2019Date of Patent: October 20, 2020Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventor: Karel Ptacek
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Patent number: 10637468Abstract: An illustrative embodiment of an integrated circuit configured for galvanically isolated signaling includes a transfer conductor carrying a modulated carrier signal. A floating transfer loop is electromagnetically coupled to the transfer conductor to receive the modulated carrier signal. The floating transfer loop includes a primary of a step-up transformer. A receiver is coupled to a secondary of the step-up transformer to receive the modulated carrier signal in an amplified, differential fashion, and to demodulate the modulated carrier signal to obtain a digital receive signal.Type: GrantFiled: October 23, 2017Date of Patent: April 28, 2020Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Karel Ptacek, Richard Scott Burton
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Patent number: 10630276Abstract: A simple, fast, easily designed circuit for demodulating a PWM signal produces an output signal indicating a duty cycle of a received PWM signal. The circuit may include a low pass filter circuit to receive a Pulse Width Modulated (PWM) signal and produce a triangular signal, a track-and-hold circuit to receive the PWM signal and the triangular signal and produce a minimum and maximum signals corresponding to minimum and maximum values of the triangular signal during each cycle of the PWM signal, and an averaging circuit to receive the minimum signal and the maximum signal and produce, by averaging the values of the minimum signal and the maximum signal, the output signal.Type: GrantFiled: September 12, 2018Date of Patent: April 21, 2020Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventor: Karel Ptacek
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Publication number: 20200083876Abstract: A simple, fast, easily designed circuit for demodulating a PWM signal produces an output signal indicating a duty cycle of a received PWM signal. The circuit may include a low pass filter circuit to receive a Pulse Width Modulated (PWM) signal and produce a triangular signal, a track-and-hold circuit to receive the PWM signal and the triangular signal and produce a minimum and maximum signals corresponding to minimum and maximum values of the triangular signal during each cycle of the PWM signal, and an averaging circuit to receive the minimum signal and the maximum signal and produce, by averaging the values of the minimum signal and the maximum signal, the output signal.Type: ApplicationFiled: September 12, 2018Publication date: March 12, 2020Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventor: Karel PTACEK
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Publication number: 20190319087Abstract: In accordance with an embodiment, an electrical element includes a first portion of a first dielectric material between a first portion of a first electrical conductor and a first portion of a second electrical conductor and a second portion of the first dielectric material between a second portion of the first electrical conductor and a first portion of a third electrical conductor. In accordance with another embodiment, an electrical component has a plurality of dopant regions formed in a semiconductor material, where the dopant regions include a plurality of dopant regions formed in a dopant region of the same conductivity type. A plurality of dopant regions of an opposite conductivity type are formed in corresponding dopant regions of the first conductivity type. A metallization system is formed over the semiconductor material, where a portion of the metallization system contacts the semiconductor material.Type: ApplicationFiled: June 24, 2019Publication date: October 17, 2019Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Richard Scott BURTON, Karel PTACEK
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Patent number: 10432098Abstract: A synchronous rectifier controller includes an exception timer, one or more blanking timers, and control logic. The control logic may detect a beginning of a conduction phase using a current sense signal. In response to detecting the beginning of the conduction phase, the control logic commences the exception timer, commences a first blanking interval, and asserts the drive signal. In response to an OFF condition being detected, the first blanking interval being elapsed, and the exception timer being running, the control logic de-asserts the drive signal and commences a second blanking interval. In response to an ON condition being detected, the second blanking interval being elapsed, and the exception timer being running, the control logic commences a third blanking interval and asserts the drive signal. The control logic may assert and de-assert the drive signal multiple times while the exception timer is running.Type: GrantFiled: July 19, 2018Date of Patent: October 1, 2019Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Karel Ptacek, Tomas Tichy
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Patent number: 10411086Abstract: In accordance with an embodiment, a method of manufacturing an electrical component that may include a high voltage capacitor that includes providing a semiconductor material of a second conductivity type in which first doped region of a first conductivity type is formed. A plurality of doped regions of the first conductivity type and a plurality of doped regions of the second conductivity type are formed in the first doped region. A first p-n junction is formed between first doped regions of the first and second conductivity types and a second p-n junction is formed between second doped regions of the first and second conductivity types. A metallization system is formed above the doped regions so that capacitors are formed by a parallel connection of a first metal layer to a polysilicon layer and the first metal layer to a second metal layer.Type: GrantFiled: March 20, 2015Date of Patent: September 10, 2019Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Richard Scott Burton, Karel Ptacek
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Publication number: 20190207603Abstract: A pull-down circuit includes a control circuit generating an activation signal in response to a supply voltage, a first reference voltage, and a feedback signal, and a charge pump configured to generate a control signal in response to the activation signal and control a switching device using the control signal. The switching device is a field-effect transistor (FET) and is coupled to a power switch and pulls down a voltage level of a gate of the power switch to prevent a premature turn-on of the power switch.Type: ApplicationFiled: March 7, 2019Publication date: July 4, 2019Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventor: Karel PTACEK
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Patent number: 10270440Abstract: An output driver includes a switching device having a first node coupled to a gate of a power switch and pulling down a voltage level of the gate of the power switch to prevent a premature turn-on of the power switch. A pull-down circuit is coupled to the switching device and keeping the switching device from being turned on to prevent the premature turn-on of the power switch.Type: GrantFiled: July 20, 2016Date of Patent: April 23, 2019Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventor: Karel Ptacek
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Publication number: 20180323719Abstract: A synchronous rectifier controller includes an exception timer, one or more blanking timers, and control logic. The control logic may detect a beginning of a conduction phase using a current sense signal. In response to detecting the beginning of the conduction phase, the control logic commences the exception timer, commences a first blanking interval, and asserts the drive signal. In response to an OFF condition being detected, the first blanking interval being elapsed, and the exception timer being running, the control logic de-asserts the drive signal and commences a second blanking interval. In response to an ON condition being detected, the second blanking interval being elapsed, and the exception timer being running, the control logic commences a third blanking interval and asserts the drive signal. The control logic may assert and de-assert the drive signal multiple times while the exception timer is running.Type: ApplicationFiled: July 19, 2018Publication date: November 8, 2018Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Karel PTACEK, Tomas TICHY
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Patent number: 10097097Abstract: A method and synchronous rectifier controller uses minimum off and on time blanking to avoid switching the switching transistor at incorrect times responsive to transients in the current sense signal. The minimum off time timer is commenced only when the current sense signal is above a reset threshold, and is reset when the current sense voltage falls below the reset threshold. Resetting the minimum off time timer in this manner avoids false starts of the minimum off time timer due to transients and allows the SRC to properly synchronize with the conduction and blocking phases of rectifier operation.Type: GrantFiled: April 30, 2014Date of Patent: October 9, 2018Assignee: Semiconductor Components Industries, LLCInventors: Tomas Tichy, Karel Ptacek
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Patent number: 10063154Abstract: A power conversion circuit including an SR MOSFET is provided. A minimum off-time timer for the SR MOSFET is started. A voltage potential at a first terminal of the SR MOSFET is measured. The SR MOSFET is turned on after a rate of change over time of the voltage potential exceeds a first threshold and before the minimum off-time timer expires.Type: GrantFiled: April 29, 2016Date of Patent: August 28, 2018Assignee: Semiconductor Components Industries, LLCInventors: Karel Ptacek, Tomas Tichy
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Publication number: 20180240761Abstract: Coupled resonators for galvanically isolated signaling between integrated circuit modules. An illustrative system embodiment includes first and second integrated circuits. The first integrated circuit includes: a transmitter that produces a modulated carrier signal on a primary conductor; a first transfer conductor connected to a first connection terminal; and a first floating loop electromagnetically coupled to the primary conductor and to the transfer conductor to convey the modulated carrier. The second integrated circuit includes: a second transfer conductor connected to a second connection terminal, the second connection terminal being electrically connected to the first connection terminal; a receiver that demodulates the modulated carrier signal; and a second floating loop electromagnetically coupled to the second transfer conductor and to the receiver to convey the modulated carrier signal to the receiver.Type: ApplicationFiled: April 19, 2018Publication date: August 23, 2018Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Richard Scott BURTON, Karel PTACEK
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Patent number: 10050541Abstract: A synchronous rectifier controller includes an exception timer, one or more blanking timers, and control logic. The control logic may detect a beginning of a conduction phase using a current sense signal. In response to detecting the beginning of the conduction phase, the control logic commences the exception timer, commences a first blanking interval, and asserts the drive signal. In response to an OFF condition being detected, the first blanking interval being elapsed, and the exception timer being running, the control logic de-asserts the drive signal and commences a second blanking interval. In response to an ON condition being detected, the second blanking interval being elapsed, and the exception timer being running, the control logic commences a third blanking interval and asserts the drive signal. The control logic may assert and de-assert the drive signal multiple times while the exception timer is running.Type: GrantFiled: November 3, 2017Date of Patent: August 14, 2018Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Karel Ptacek, Tomas Tichy
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Patent number: 10008457Abstract: Coupled resonators for galvanically isolated signaling between integrated circuit modules. An illustrative multi-module integrated circuit comprises: a transmitter in a first module, the transmitter providing a modulated carrier signal; a receiver in a second module demodulating the modulated carrier signal; and a galvanically isolated signaling path that includes: a first integrated resonator in the first module and a second integrated resonator in the second module, the first and second integrated resonators being resonantly coupled to convey the modulated carrier signal from the transmitter to the receiver.Type: GrantFiled: October 18, 2016Date of Patent: June 26, 2018Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Richard Scott Burton, Karel Ptacek
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Patent number: 9973091Abstract: A switched mode power supply, in some embodiments, comprises a synchronous rectification transistor switch including a gate, and it further comprises an output driver coupled to the gate and providing a driving signal to the gate. The driving signal is determined based on a dynamically controllable clamp signal and a prior driving signal.Type: GrantFiled: January 14, 2015Date of Patent: May 15, 2018Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Karel Ptacek, Tomas Tichy