Patents by Inventor Karen E. Moore
Karen E. Moore has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10825924Abstract: A semiconductor device includes a semiconductor substrate configured to include a channel, a gate supported by the semiconductor substrate to control current flow through the channel, a first dielectric layer supported by the semiconductor substrate and including an opening in which the gate is disposed, and a second dielectric layer disposed between the first dielectric layer and a surface of the semiconductor substrate in a first area over the channel. The gate may be configured to include a lateral overhang that is separated from an upper surface of the first dielectric layer.Type: GrantFiled: July 17, 2017Date of Patent: November 3, 2020Assignee: NXP USA, Inc.Inventors: Bruce M. Green, Darrell G. Hill, Karen E. Moore
-
Patent number: 10541324Abstract: An embodiment of a semiconductor device includes a semiconductor substrate that includes a host substrate, a buffer layer that includes at least one additional layer formed over the substrate, a channel layer formed over the buffer layer, a barrier layer formed over the channel layer forming a channel, a gate electrode disposed over the substrate electrically coupled to the channel, and an ohmic contact recessed into the barrier layer. A method for fabricating the semiconductor device includes forming a semiconductor substrate that includes a mixed crystal layer, creating an isolation region that defines an active region along an upper surface of the semiconductor substrate, forming a gate electrode over the semiconductor substrate in the active region, and recessing an ohmic contact into the semiconductor substrate.Type: GrantFiled: June 19, 2017Date of Patent: January 21, 2020Assignee: NXP USA, Inc.Inventors: Bruce M. Green, Darrell G. Hill, Karen E. Moore
-
Patent number: 10522670Abstract: A semiconductor device includes a semiconductor substrate configured to include a channel, a gate supported by the semiconductor substrate to control current flow through the channel, a first dielectric layer supported by the semiconductor substrate and including an opening in which the gate is disposed, and a second dielectric layer disposed between the first dielectric layer and a surface of the semiconductor substrate in a first area over the channel. The second dielectric layer is patterned such that the first dielectric layer is disposed on the surface of the semiconductor substrate in a second area over the channel.Type: GrantFiled: May 4, 2017Date of Patent: December 31, 2019Assignee: NXP USA, Inc.Inventors: Bruce M. Green, Darrell G. Hill, Karen E. Moore
-
Publication number: 20170317202Abstract: A semiconductor device includes a semiconductor substrate configured to include a channel, a gate supported by the semiconductor substrate to control current flow through the channel, a first dielectric layer supported by the semiconductor substrate and including an opening in which the gate is disposed, and a second dielectric layer disposed between the first dielectric layer and a surface of the semiconductor substrate in a first area over the channel. The gate may be configured to include a lateral overhang that is separated from an upper surface of the first dielectric layer.Type: ApplicationFiled: July 17, 2017Publication date: November 2, 2017Inventors: Bruce M. Green, Darrell G. Hill, Karen E. Moore
-
Patent number: 9799760Abstract: A semiconductor device includes a semiconductor substrate configured to include a channel, first and second ohmic contacts supported by the semiconductor substrate, in ohmic contact with the semiconductor substrate, and spaced from one another for current flow between the first and second ohmic contacts through the channel, and first and second dielectric layers supported by the semiconductor substrate. At least one of the first and second ohmic contacts extends through respective openings in the first and second dielectric layers. The second dielectric layer is disposed between the first dielectric layer and a surface of the semiconductor substrate, and the second dielectric layer includes a wet etchable material having an etch selectivity to a dry etchant of the first dielectric layer.Type: GrantFiled: August 17, 2015Date of Patent: October 24, 2017Assignee: NXP USA, INC.Inventors: Bruce M. Green, Darrell G. Hill, Jenn Hwa Huang, Karen E. Moore
-
Publication number: 20170294531Abstract: An embodiment of a semiconductor device includes a semiconductor substrate that includes an upper surface and a channel, a gate electrode disposed over the substrate electrically coupled to the channel, and a Schottky metal layer disposed over the substrate adjacent the gate electrode. The Schottky metal layer includes a Schottky contact electrically coupled to the channel which provides a Schottky junction and at least one alignment mark disposed over the semiconductor substrate. A method for fabricating the semiconductor device includes creating an isolation region that defines an active region along an upper surface of a semiconductor substrate, forming a gate electrode over the semiconductor substrate in the active region, and forming a Schottky metal layer over the semiconductor substrate. Forming the Schottky metal layer includes forming at least one Schottky contact electrically coupled to the channel and providing a Schottky junction, and forming an alignment mark in the isolation region.Type: ApplicationFiled: June 19, 2017Publication date: October 12, 2017Inventors: Bruce M. Green, Darrell G. Hill, Karen E. Moore
-
Publication number: 20170236929Abstract: A semiconductor device includes a semiconductor substrate configured to include a channel, a gate supported by the semiconductor substrate to control current flow through the channel, a first dielectric layer supported by the semiconductor substrate and including an opening in which the gate is disposed, and a second dielectric layer disposed between the first dielectric layer and a surface of the semiconductor substrate in a first area over the channel. The second dielectric layer is patterned such that the first dielectric layer is disposed on the surface of the semiconductor substrate in a second area over the channel.Type: ApplicationFiled: May 4, 2017Publication date: August 17, 2017Inventors: Bruce M. Green, Darrell G. Hill, Karen E. Moore
-
Patent number: 9685345Abstract: An embodiment of a semiconductor device includes a semiconductor substrate that includes an upper surface and a channel, a gate electrode disposed over the substrate electrically coupled to the channel, and a Schottky metal layer disposed over the substrate adjacent the gate electrode. The Schottky metal layer includes a Schottky contact electrically coupled to the channel which provides a Schottky junction and at least one alignment mark disposed over the semiconductor substrate. A method for fabricating the semiconductor device includes creating an isolation region that defines an active region along an upper surface of a semiconductor substrate, forming a gate electrode over the semiconductor substrate in the active region, and forming a Schottky metal layer over the semiconductor substrate. Forming the Schottky metal layer includes forming at least one Schottky contact electrically coupled to the channel and providing a Schottky junction, and forming an alignment mark in the isolation region.Type: GrantFiled: November 19, 2013Date of Patent: June 20, 2017Assignee: NXP USA, INC.Inventors: Bruce M. Green, Darrell G. Hill, Karen E. Moore
-
Patent number: 9281204Abstract: A semiconductor device is provided which includes a GaN-on-SiC substrate (50-51) and a multi-layer passivation stack (52-54) in which patterned step openings (76) are defined and filled with gate metal layers using a lift-off gate metal process to form a T-gate electrode (74) as a stepped gate electrode having sidewall extensions and a contact base portion with one or more gate ledges.Type: GrantFiled: April 23, 2014Date of Patent: March 8, 2016Assignee: Freescale Semiconductor, Inc.Inventors: Karen E. Moore, Bruce M. Green
-
Patent number: 9276101Abstract: A low leakage current switch device (110) is provided which includes a GaN-on-Si substrate (11-43) covered by a passivation surface layer (43) in which a T-gate electrode with sidewall extensions (48) is formed and coated with a conformal passivation layer (49) so that the T-gate electrode sidewall extensions are spaced apart from the underlying passivation surface layer (43) by the conformal passivation layer (49).Type: GrantFiled: June 26, 2015Date of Patent: March 1, 2016Assignee: Freescale Semiconductor, Inc.Inventors: Bruce M. Green, Karen E. Moore, Olin Hartin
-
Publication number: 20150357452Abstract: A semiconductor device includes a semiconductor substrate configured to include a channel, first and second ohmic contacts supported by the semiconductor substrate, in ohmic contact with the semiconductor substrate, and spaced from one another for current flow between the first and second ohmic contacts through the channel, and first and second dielectric layers supported by the semiconductor substrate. At least one of the first and second ohmic contacts extends through respective openings in the first and second dielectric layers. The second dielectric layer is disposed between the first dielectric layer and a surface of the semiconductor substrate, and the second dielectric layer includes a wet etchable material having an etch selectivity to a dry etchant of the first dielectric layer.Type: ApplicationFiled: August 17, 2015Publication date: December 10, 2015Inventors: Bruce M. Green, Darrell G. Hill, Jenn Hwa Huang, Karen E. Moore
-
Publication number: 20150311084Abstract: A semiconductor device is provided which includes a GaN-on-SiC substrate (50-51) and a multi-layer passivation stack (52-54) in which patterned step openings (76) are defined and filled with gate metal layers using a lift-off gate metal process to form a T-gate electrode (74) as a stepped gate electrode having sidewall extensions and a contact base portion with one or more gate ledges.Type: ApplicationFiled: April 23, 2014Publication date: October 29, 2015Applicant: Freescale Semiconductor, Inc.Inventors: Karen E. Moore, Bruce M. Green
-
Publication number: 20150295075Abstract: A low leakage current switch device (110) is provided which includes a GaN-on-Si substrate (11-43) covered by a passivation surface layer (43) in which a T-gate electrode with sidewall extensions (48) is formed and coated with a conformal passivation layer (49) so that the T-gate electrode sidewall extensions are spaced apart from the underlying passivation surface layer (43) by the conformal passivation layer (49).Type: ApplicationFiled: June 26, 2015Publication date: October 15, 2015Applicant: Freescale Semiconductor, Inc.Inventors: Bruce M. Green, Karen E. Moore, Olin Hartin
-
Patent number: 9153448Abstract: A semiconductor device includes a semiconductor substrate configured to include a channel, a gate supported by the semiconductor substrate to control current flow through the channel, a first dielectric layer supported by the semiconductor substrate and including an opening in which the gate is disposed, and a second dielectric layer disposed between the first dielectric layer and a surface of the semiconductor substrate in a first area over the channel. The second dielectric layer is patterned such that the first dielectric layer is disposed on the surface of the semiconductor substrate in a second area over the channel.Type: GrantFiled: January 21, 2015Date of Patent: October 6, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Bruce M. Green, Darrell G. Hill, Jenn Hwa Huang, Karen E. Moore
-
Patent number: 9123645Abstract: Embodiments include methods of making semiconductor devices with low leakage Schottky contacts. An embodiment includes providing a partially completed semiconductor device including a substrate, a semiconductor on the substrate, and a passivation layer on the semiconductor, and using a first mask, locally etching the passivation layer to expose a portion of the semiconductor. Without removing the first mask, a Schottky contact is formed of a first material on the exposed portion of the semiconductor, and the mask is removed. Using a further mask, a step-gate conductor of a second material electrically coupled to the Schottky contact is formed overlying parts of the passivation layer adjacent to the Schottky contact. By minimizing the process steps between opening the Schottky contact window in the passivation layer and forming the Schottky contact material in this window, the gate leakage of a resulting field effect device having a Schottky gate may be substantially reduced.Type: GrantFiled: November 21, 2013Date of Patent: September 1, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Bruce M. Green, Haldane S. Henry, Chun-Li Liu, Karen E. Moore, Matthias Passlack
-
Patent number: 9111868Abstract: A semiconductor device includes a semiconductor substrate configured to include a channel, first and second ohmic contacts supported by the semiconductor substrate, in ohmic contact with the semiconductor substrate, and spaced from one another for current flow between the first and second ohmic contacts through the channel, and first and second dielectric layers supported by the semiconductor substrate. At least one of the first and second ohmic contacts extends through respective openings in the first and second dielectric layers. The second dielectric layer is disposed between the first dielectric layer and a surface of the semiconductor substrate, and the second dielectric layer includes a wet etchable material having an etch selectivity to a dry etchant of the first dielectric layer.Type: GrantFiled: June 26, 2012Date of Patent: August 18, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Bruce M. Green, Darrell G. Hill, Jenn Hwa Huang, Karen E. Moore
-
Patent number: 9099433Abstract: A low leakage current switch device (110) is provided which includes a GaN-on-Si substrate (11-13) covered by a passivation surface layer (43) in which a T-gate electrode with sidewall extensions (48) is formed and coated with a conformal passivation layer (49) so that the T-gate electrode sidewall extensions are spaced apart from the underlying passivation surface layer (43) by the conformal passivation layer (49).Type: GrantFiled: April 23, 2012Date of Patent: August 4, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Bruce M. Green, Karen E. Moore, Olin Hartin
-
Publication number: 20150137135Abstract: An embodiment of a semiconductor device includes a semiconductor substrate that includes an upper surface and a channel, a gate electrode disposed over the substrate electrically coupled to the channel, and a Schottky metal layer disposed over the substrate adjacent the gate electrode. The Schottky metal layer includes a Schottky contact electrically coupled to the channel which provides a Schottky junction and at least one alignment mark disposed over the semiconductor substrate. A method for fabricating the semiconductor device includes creating an isolation region that defines an active region along an upper surface of a semiconductor substrate, forming a gate electrode over the semiconductor substrate in the active region, and forming a Schottky metal layer over the semiconductor substrate. Forming the Schottky metal layer includes forming at least one Schottky contact electrically coupled to the channel and providing a Schottky junction, and forming an alignment mark in the isolation region.Type: ApplicationFiled: November 19, 2013Publication date: May 21, 2015Inventors: BRUCE M. GREEN, DARRELL G. HILL, KAREN E. MOORE
-
Publication number: 20150132932Abstract: A semiconductor device includes a semiconductor substrate configured to include a channel, a gate supported by the semiconductor substrate to control current flow through the channel, a first dielectric layer supported by the semiconductor substrate and including an opening in which the gate is disposed, and a second dielectric layer disposed between the first dielectric layer and a surface of the semiconductor substrate in a first area over the channel. The second dielectric layer is patterned such that the first dielectric layer is disposed on the surface of the semiconductor substrate in a second area over the channel.Type: ApplicationFiled: January 21, 2015Publication date: May 14, 2015Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Bruce M. Green, Darrell G. Hill, Jenn Hwa Huang, Karen E. Moore
-
Patent number: 8946776Abstract: A semiconductor device includes a semiconductor substrate configured to include a channel, a gate supported by the semiconductor substrate to control current flow through the channel, a first dielectric layer supported by the semiconductor substrate and including an opening in which the gate is disposed, and a second dielectric layer disposed between the first dielectric layer and a surface of the semiconductor substrate in a first area over the channel. The second dielectric layer is patterned such that the first dielectric layer is disposed on the surface of the semiconductor substrate in a second area over the channel.Type: GrantFiled: June 26, 2012Date of Patent: February 3, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Bruce M. Green, Darrell G. Hill, Jenn Hwa Huang, Karen E. Moore