Abstract: Embodiments include methods of making semiconductor devices with low leakage Schottky contacts. An embodiment includes providing a partially completed semiconductor device including a substrate, a semiconductor on the substrate, and a passivation layer on the semiconductor, and using a first mask, locally etching the passivation layer to expose a portion of the semiconductor. Without removing the first mask, a Schottky contact is formed of a first material on the exposed portion of the semiconductor, and the mask is removed. Using a further mask, a step-gate conductor of a second material electrically coupled to the Schottky contact is formed overlying parts of the passivation layer adjacent to the Schottky contact. By minimizing the process steps between opening the Schottky contact window in the passivation layer and forming the Schottky contact material in this window, the gate leakage of a resulting field effect device having a Schottky gate may be substantially reduced.

Abstract: A semiconductor device includes a semiconductor substrate configured to include a channel, first and second ohmic contacts supported by the semiconductor substrate, in ohmic contact with the semiconductor substrate, and spaced from one another for current flow between the first and second ohmic contacts through the channel, and first and second dielectric layers supported by the semiconductor substrate. At least one of the first and second ohmic contacts extends through respective openings in the first and second dielectric layers. The second dielectric layer is disposed between the first dielectric layer and a surface of the semiconductor substrate, and the second dielectric layer includes a wet etchable material having an etch selectivity to a dry etchant of the first dielectric layer.

Abstract: A semiconductor device includes a semiconductor substrate configured to include a channel, a gate supported by the semiconductor substrate to control current flow through the channel, a first dielectric layer supported by the semiconductor substrate and including an opening in which the gate is disposed, and a second dielectric layer disposed between the first dielectric layer and a surface of the semiconductor substrate in a first area over the channel. The second dielectric layer is patterned such that the first dielectric layer is disposed on the surface of the semiconductor substrate in a second area over the channel.

Abstract: Embodiments include semiconductor devices with low leakage Schottky contacts. An embodiment is formed by providing a partially completed semiconductor device including a substrate, a semiconductor on the substrate, and a passivation layer on the semiconductor, and using a first mask, locally etching the passivation layer to expose a portion of the semiconductor. Without removing the first mask, a Schottky contact is formed of a first material on the exposed portion of the semiconductor, and the first mask is removed. Using a further mask, a step-gate conductor of a second material electrically coupled to the Schottky contact is formed overlying parts of the passivation layer adjacent to the Schottky contact. By minimizing the process steps between opening the Schottky contact window in the passivation layer and forming the Schottky contact material in this window, the gate leakage of a resulting field effect device having a Schottky gate may be substantially reduced.

Abstract: A low leakage current switch device (110) is provided which includes a GaN-on-Si substrate (11-13) covered by a passivation surface layer (43) in which a T-gate electrode with sidewall extensions (48) is formed and coated with a conformal passivation layer (49) so that the T-gate electrode sidewall extensions are spaced apart from the underlying passivation surface layer (43) by the conformal passivation layer (49).

Abstract: A dielectric layer for a gallium nitride transistor is disclosed. In one example, the dielectric layer has a hydrogen content of less than or equal to 10% by atomic percentage. In one example, both a dielectric layer formed before a conductive electrode of the transistor and a dielectric layer formed after the conductive elective electrode have a hydrogen content of less than or equal to 10% by atomic percentage. In one example, the dielectric layer formed before the conductive electrode is formed by a LPCVD process and the dielectric layer formed after the conductive electrode is formed by a sputtering process.

Abstract: Embodiments include semiconductor devices with low leakage Schottky contacts. An embodiment is formed by providing a partially completed semiconductor device including a substrate, a semiconductor on the substrate, and a passivation layer on the semiconductor, and using a first mask, locally etching the passivation layer to expose a portion of the semiconductor. Without removing the first mask, a Schottky contact is formed of a first material on the exposed portion of the semiconductor, and the first mask is removed. Using a further mask, a step-gate conductor of a second material electrically coupled to the Schottky contact is formed overlying parts of the passivation layer adjacent to the Schottky contact. By minimizing the process steps between opening the Schottky contact window in the passivation layer and forming the Schottky contact material in this window, the gate leakage of a resulting field effect device having a Schottky gate may be substantially reduced.

Abstract: Methods and apparatus are described for semiconductor devices. A method comprises providing a partially completed semiconductor device including a substrate, a semiconductor on the substrate, and a passivation layer on the semiconductor, and using a first mask, locally etching the passivation layer to expose a portion of the semiconductor, and without removing the first mask, forming a Schottky contact of a first material on the exposed portion of the semiconductor, then removing the first mask, and using a further mask, forming a step-gate conductor of a second material electrically coupled to the Schottky contact and overlying parts of the passivation layer adjacent to the Schottky contact. By minimizing the process steps between opening the Schottky contact window in the passivation layer and forming the Schottky contact material in this window, the gate leakage of a resulting field effect device having a Schottky gate may be substantially reduced.

Abstract: Method and apparatus are described for semiconductor devices. The method (100) comprises, providing a partially completed semiconductor device (31-1) including a substrate (21), a semiconductor (22) on the substrate (21) and a passivation layer (25) on the semiconductor (22), and using a first mask (32), locally etching the passivation layer (25) to expose a portion (36) of the semiconductor (22), and without removing the first mask (32) forming a Schottky contact (42-1) of a first material on the exposed portion (36) of the semiconductor (22), then removing the first mask (32) and using a further mask (44), forming a step-gate conductor (48-1) of a second material electrically coupled to the Schottky contact (42-1) and overlying parts (25-1) of the passivation layer (25) adjacent to the Schottky contact (42-1).

Abstract: An alignment mark (51) is formed on the surface (64) of a silicon carbide substrate (50). The alignment mark (51) is used to reflect a light signal (72) to determine the proper position for the silicon carbide substrate (50). The materials that are used to form the alignment mark (51) can be used to form an alignment mark on any transparent or semi-transparent substrate and will maintain physical integrity through very high temperature processing steps.

Abstract: A silicon carbide transistor (10) is formed from a silicon carbide film (14) that is formed on a silicon carbide substrate bulk (37). A conductor pattern layer (25) is formed on the silicon carbide film (14) and the silicon carbide film (14) removed from the silicon carbide substrate bulk (37) and attached to a substrate (11) of a dissimilar semiconductor material.

Abstract: A method of performing electron beam lithography on high resistivity substrates including forming semiconductor material on a high resistivity substrate and etching the semiconductor material to form mesas with electrically interconnecting bridges between the mesas. Semiconductor devices are formed in the mesas employing electron beam lithography and charges generated by the electron beam lithography are dispersed along the interconnecting bridges thereby preventing charge accumulation on the mesas. The bridges are removed by etching or sawing during die separation.

Abstract: An alignment mark (51) is formed on the surface (64) of a silicon carbide substrate (50). The alignment mark (51) is used to reflect a light signal (72) to determine the proper position for the silicon carbide substrate (50). The materials that are used to form the alignment mark (51) can be used to form an alignment mark on any transparent or semi-transparent substrate and will maintain physical integrity through very high temperature processing steps.

Abstract: A silicon carbide MESFET (10) is formed to have a source (21) and a drain (22) that are self-aligned to a gate (16) of the MESFET (10). The gate (16) is formed to have a T-shaped structure with a gate-to-source spacer (18) and gate-to-drain spacer (19) along each side of a base of the gate (16). The gate (16) is used as a mask for implanting dopants to form the source (21) and drain (22). A laser annealing is performed after the implantation to activate the dopants. Because the laser annealing is a low temperature operation, the gate (16) is not detrimentally affected during the annealing.

Abstract: A method of fabricating a semiconductor device on thinned wide bandgap material including providing a support having a planar surface and a semiconductor substrate. Implanting a layer of ions in the substrate to create a layer of microbubbles defining a thin film having a planar surface and a remaining mass separated by the layer of implanted ions. Intimately contacting the planar surface of the thin film to the planar surface of the support and heating the support and substrate to separate the remaining mass from the thin film. A semiconductor device is formed on the thin film, and the support is thinned.

Abstract: A silicon carbide MESFET (10) is formed to have a source (21) and a drain (22) that are self-aligned to a gate (16) of the MESFET (10). The gate (16) is formed to have a T-shaped structure with a gate-to-source spacer (18) and gate-to-drain spacer (19) along each side of a base of the gate (16). The gate (16) is used as a mask for implanting dopants to form the source (21) and drain (22). A laser annealing is performed after the implantation to activate the dopants. Because the laser annealing is a low temperature operation, the gate (16) is not detrimentally affected during the annealing.

Abstract: A lateral MESFET (10,20) utilizes a drain (17) and a source (18) damage termination layer to improve the breakdown voltage of the MESFET (10,20). The source (18) and drain (17) damage termination layers are very shallow to prevent interfering with lateral current flow in the channel layer (12). The source (18) and drain (17) damage termination layers are formed by implanting large inert ions using high implant doses and low implantation energies.

Abstract: An implant mask (14) and an etch mask (16) are utilized in forming a silicon carbide JFET (10). A source opening (17) and a drain opening (18) are formed in the masks (14,16). The etch mask (16) is removed, and a source area (19) and a drain area 21 are implanted through the openings (17,18) and source and drain contact (23, 24) are formed. A protective layer (26) is used to form source and drain contacts (23,24). A gate contact (27) is utilized to ensure the gate (28) is self-aligned to the gate contact (27).