Patents by Inventor Karin Strauss

Karin Strauss has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160371434
    Abstract: A database implemented by storing information encoded in DNA molecules provides high information density but the information is more difficult to access than in conventional electronic storage media. A relational database is a way of organizing information by using multiple related tables. Relational algebra operations are performed on relational databases to locate and manipulate information. This disclosure provides techniques for implementing relational algebra operations on a relational database that uses DNA molecules to store information. The techniques of this disclosure relate to the structure of DNA molecules used to store the information and to correlations between relational algebra operations and manipulations of DNA molecules.
    Type: Application
    Filed: June 16, 2015
    Publication date: December 22, 2016
    Inventors: Karin Strauss, Benjamin G. Zorn, Kris K. Ganjam
  • Patent number: 9471532
    Abstract: A multi-core processor with a shared physical memory is described. In an embodiment a sending core sends a memory write request to a destination core so that the request may be acted upon by the destination core as if it originated from the destination core. In an example, a data structure is configured in the shared physical memory and mapped to be accessible to the sending and destination cores. In an example, the shared data structure is used as a message channel between the sending and destination cores to carry data using the memory write request. In an embodiment a notification mechanism is enabled using the shared physical memory in order to notify the destination core of events by updating a notification data structure. In an example, the notification mechanism triggers a notification process at the destination core to inform a receiving process of a notification.
    Type: Grant
    Filed: February 11, 2011
    Date of Patent: October 18, 2016
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Richard John Black, Timothy Harris, Ross Cameron McIlroy, Karin Strauss
  • Patent number: 9442799
    Abstract: A memory controller can include an error correction module for extended lifetime memory that tracks at least one sized block of non-fault consecutive bits within the disabled page as spare blocks and reuses the spare blocks from the disabled pages as an error correction resource for active blocks. The active blocks can store data, data and metadata, or metadata only (e.g., error correction metadata). A method for extended lifetime memory can include, for an active block of metadata containing at least one fault, using at least one spare block to correct the data of the active block. For an active block of data containing at least one fault, the data can be initially corrected via XOR correction with a first spare block and then ultimately corrected via XOR correction with a second spare block.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: September 13, 2016
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Mark Steven Manasse, Sergey Yekhanin, Parikshit S. Gopalan, Karin Strauss, John D. Davis
  • Publication number: 20160254063
    Abstract: A memory chip for dynamic approximate storage includes an array of memory cells associated with at least two regions. The chip further includes at least one threshold register for storing values for thresholds for memory cells corresponding to each of the at least two regions; and control logic to programmatically adjust the values for the thresholds for the memory cells. A method of controlling a storage device for dynamic approximate storage includes modifying at least one value stored in a threshold register and associated with at least one cell in a region of a memory comprising at least two regions to apply a biasing for the at least one cell, wherein the biasing adjusts ranges for values in a cell.
    Type: Application
    Filed: February 27, 2015
    Publication date: September 1, 2016
    Inventors: KARIN STRAUSS, LUIS HENRIQUE CEZE, HENRIQUE S. MALVAR, QING GUO
  • Publication number: 20160253238
    Abstract: A method of encoding data on single level or variable multi-level cell storage includes receiving a block of encoded data from an approximation-aware application and at least an importance attribute associated with the block of encoded data; and assigning the block of encoded data to a memory address or a particular region of a memory having at least three precision levels, based at least according to the importance attribute. The importance attribute indicates a relative sensitivity of bits of the block to errors in an output quality from decoding the encoded data. An approximation-aware application can be an image encoding application having a modified entropy encoding step that enables identification and splitting of bits into groupings according to sensitivity to errors.
    Type: Application
    Filed: February 27, 2015
    Publication date: September 1, 2016
    Inventors: KARIN STRAUSS, LUIS HENRIQUE CEZE, HENRIQUE S. MALVAR, QING GUO
  • Patent number: 9412466
    Abstract: The present technology relaxes the precision (or full data-correctness-guarantees) requirements in memory operations, such as writing or reading, of MLC memories so that an application may write and read a digital data value as an approximate value. Types of MLCs include Flash MLC and MLC Phase Change Memory (PCM) as well as other resistive technologies. Many software applications may not need the accuracy or precision typically used to store and read data values. For example, an application may render an image on a relatively low resolution display and may not need an accurate data value for each pixel. By relaxing the precision or correctness requirements is a memory operation, MLC memories may have increased performance, lifetime, density, and/or energy efficiency.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: August 9, 2016
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Karin Strauss, Douglas C. Burger, Luis Henrique Ceze, Adrian Sampson
  • Publication number: 20160170830
    Abstract: A codeword is generated from a message. One or more anchor values are appended to the codeword at predetermined anchor positions. Before the codeword is stored in a memory block, the locations and values of stuck cells in the memory block are determined. Based on the values and positions of the stuck cells, the values of the codeword are remapped so that values of the codeword that are the same as the values of the stuck cells are placed at the positions of the stuck cells. The remapped codeword is stored in the memory block. When the message is later read, the original codeword can be recovered from the remapped codeword based on the locations of the anchor values in the remapped codeword.
    Type: Application
    Filed: February 1, 2016
    Publication date: June 16, 2016
    Inventors: John D. Davis, Parikshit Gopalan, Mark Manasse, Karin Strauss, Sergey Yekhanin
  • Patent number: 9367519
    Abstract: Various embodiments relating to encoding a sparse matrix into a data structure format that may be efficiently processed via parallel processing of a computing system are provided. In one embodiment, a sparse matrix may be received. A set of designated rows of the sparse matrix may be traversed until all non-zero elements in the sparse matrix have been placed in a first array. Each time a row in the set is traversed, a next non-zero element in that row may be placed in the first array. If all non-zero elements for a given row of the set of designated rows have been placed in the first array, the given row may be replaced in the set of designated rows with a next unprocessed row of the sparse matrix. The data structure in which the sparse matrix is encoded may be outputted. The data structure may include the first array.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: June 14, 2016
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Karin Strauss, Jeremy Fowers, Kalin Ovtcharov
  • Patent number: 9280417
    Abstract: A codeword is generated from a message. One or more anchor values are appended to the codeword at predetermined anchor positions. Before the codeword is stored in a memory block, the locations and values of stuck cells in the memory block are determined. Based on the values and positions of the stuck cells, the values of the codeword are remapped so that values of the codeword that are the same as the values of the stuck cells are placed at the positions of the stuck cells. The remapped codeword is stored in the memory block. When the message is later read, the original codeword can be recovered from the remapped codeword based on the locations of the anchor values in the remapped codeword.
    Type: Grant
    Filed: May 21, 2013
    Date of Patent: March 8, 2016
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: John D. Davis, Parikshit Gopalan, Mark Manasse, Karin Strauss, Sergey Yekhanin
  • Publication number: 20150378821
    Abstract: A memory controller can include an error correction module for extended lifetime memory that tracks at least one sized block of non-fault consecutive bits within the disabled page as spare blocks and reuses the spare blocks from the disabled pages as an error correction resource for active blocks. The active blocks can store data, data and metadata, or metadata only (e.g., error correction metadata). A method for extended lifetime memory can include, for an active block of metadata containing at least one fault, using at least one spare block to correct the data of the active block. For an active block of data containing at least one fault, the data can be initially corrected via XOR correction with a first spare block and then ultimately corrected via XOR correction with a second spare block.
    Type: Application
    Filed: June 26, 2014
    Publication date: December 31, 2015
    Inventors: Mark Steven Manasse, Sergey Yekhanin, Parikshit S. Gopalan, Karin Strauss, John D. Davis
  • Publication number: 20150318870
    Abstract: Variable width error correction is described. A memory controller can determine, from a memory address, what type of error correction is to be applied for the address region of that memory address and can generate commands for the memory device. An amount of error correction metadata associated with that address region may vary depending on the spatial location of the address region. In some cases, two translations may be performed: one by a processor using information set up by an operating system and another by the memory controller (or the memory device). In other cases, a single translation may be performed, for example by a processor using information set up by the operating system, which can determine the variable error correction during translation of a virtual address region to a real physical address region.
    Type: Application
    Filed: April 30, 2014
    Publication date: November 5, 2015
    Applicant: Microsoft Corporation
    Inventors: PETER GLASKOWSKY, KARIN STRAUSS
  • Publication number: 20150227517
    Abstract: This document relates to trend response management. One example can detect a trending topic and identify content associated with the trending topic. The example can take an action relating to the content that decreases a trend-induced processing spike and/or enhances a user search experience associated with the trending topic.
    Type: Application
    Filed: February 7, 2014
    Publication date: August 13, 2015
    Applicant: Microsoft Corporation
    Inventors: Dimitrios LYMBEROPOULOS, Oriana RIVA, Karin STRAUSS, Doug Burger, Gennady PEKHIMENKO
  • Patent number: 9092357
    Abstract: Inoperable phase change memory (PCM) blocks in a PCM device are remapped to one or more operable PCM blocks, e.g. by maintaining an inoperable block table that includes an entry for each inoperable PCM block and an address of a remapped PCM block. Alternatively, the PCM blocks may be remapped by storing the address of the remapped block in the block itself, and setting a remapping bit that indicate the block has been remapped. Where the remapping is performed by a processor, an inoperable block bit may be set in a translation look aside buffer that indicates whether a virtual memory page is associated with an inoperable or remapped PCM block. When a request to access a virtual memory page is received, the processor references the inoperable block bit associated with the virtual memory page to determine whether to check for remapped PCM blocks in the inoperable block table.
    Type: Grant
    Filed: October 29, 2010
    Date of Patent: July 28, 2015
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: John D. Davis, Karin Strauss, Douglas C. Burger
  • Patent number: 9032244
    Abstract: The techniques discussed herein identify failed segments of memory in a memory region. The techniques may then manage the failed segments of memory by logically clustering the failed segments of memory at an outlying portion of the memory region using a remapping process. The remapping process may include creating and storing remapping metadata defining segment remapping entries for the memory region. Accordingly, the failure clustering logically eliminates or reduces the memory fragmentation so that a system can allocate larger portions of contiguous memory for object storage.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: May 12, 2015
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Karin Strauss, Burton J. Smith, Kathryn S. McKinley
  • Patent number: 9021313
    Abstract: A system and method are provided for enhancing approximate computing by a computer system. In one example, an interface is provided comprising a variable-identifier module and a bit-priority module. The variable-identifier module is configured to identify one or more variables of data that are to be processed by the computer system with approximate precision. Approximate precision is a precision level at which a hardware device does not guarantee full data-correctness for the one or more variables. The bit-priority module is configured to assign bit-priorities to the one or more variables. The bit-priorities include relative levels of importance among bits of each of the one or more variables. The relative levels of importance include at least high-priority bits and low-priority bits.
    Type: Grant
    Filed: November 28, 2012
    Date of Patent: April 28, 2015
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Karin Strauss, Adrian Sampson, Luis Henrique Ceze
  • Publication number: 20150067009
    Abstract: Various embodiments relating to encoding a sparse matrix into a data structure format that may be efficiently processed via parallel processing of a computing system are provided. In one embodiment, a sparse matrix may be received. A set of designated rows of the sparse matrix may be traversed until all non-zero elements in the sparse matrix have been placed in a first array. Each time a row in the set is traversed, a next non-zero element in that row may be placed in the first array. If all non-zero elements for a given row of the set of designated rows have been placed in the first array, the given row may be replaced in the set of designated rows with a next unprocessed row of the sparse matrix. The data structure in which the sparse matrix is encoded may be outputted. The data structure may include the first array.
    Type: Application
    Filed: August 30, 2013
    Publication date: March 5, 2015
    Applicant: Microsoft Corporation
    Inventors: Karin Strauss, Jeremy Fowers, Kalin Ovtcharov
  • Publication number: 20150067273
    Abstract: Various embodiments relating to performing multiple computations are provided. In one embodiment, a computing system includes an off-chip storage device configured to store a plurality of stream elements and associated tags and a computation device. The computation device includes an on-chip storage device configured to store a plurality of independently addressable resident elements, and a plurality of parallel processing units. Each parallel processing unit may be configured to receive one or more stream elements and associated tags from the off-chip storage device and select one or more resident elements from a subset of resident elements driven in parallel from the on-chip storage device. A selected resident element may be indicated by an associated tag as matching a stream element. Each parallel processing unit may be configured to perform one or more computations using the one or more stream elements and the one or more selected resident elements.
    Type: Application
    Filed: August 30, 2013
    Publication date: March 5, 2015
    Applicant: Microsoft Corporation
    Inventors: Karin Strauss, Jeremy Fowers
  • Patent number: 8972649
    Abstract: A generator matrix is provided to generate codewords from messages of write operations. Rather than generate a codeword using the entire generator matrix, some number of bits of the codeword are determined to be, or designated as, stuck bits. One or more submatrices of the generator matrix are determined based on the columns of the generator matrix that correspond to the stuck bits. The submatrices are used to generate the codeword from the message, and only the bits of the codeword that are not the stuck bits are written to a memory block. By designating one or more bits as stuck bits, the operating life of the bits is increased. Some of the submatrices of the generator matrix may be pre-computed for different stuck bit combinations. The pre-computed submatrices may be used to generate the codewords, thereby increasing the performance of write operations.
    Type: Grant
    Filed: October 5, 2012
    Date of Patent: March 3, 2015
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: John D. Davis, Parikshit Gopalan, Mark S. Manasse, Karin Strauss, Sergey Yekhanin
  • Publication number: 20150033064
    Abstract: A memory region can durably self-identify as being faulty when read. Information that would have been assigned to the faulty memory region can be assigned to another of that sized region in memory using a replacement encoding technique. For phase change memory, at least two fault states can be provided for durably self-identifying a faulty memory region; one state at a highest resistance range and the other state at a lowest resistance range. Replacement cells can be used to shift or assign data when a self-identifying memory fault is present. A memory controller and memory module, alone or in combination may manage replacement cell use and facilitate driving a newly discovered faulty cell to a fault state if the faulty cell is not already at the fault state.
    Type: Application
    Filed: July 24, 2013
    Publication date: January 29, 2015
    Applicant: Microsoft Corporation
    Inventors: John D. Davis, Karin Strauss, Mark Steven Manasse, Parikshit S. Gopalan, Sergey Yekhanin
  • Publication number: 20150009736
    Abstract: The present technology relaxes the precision (or full data-correctness-guarantees) requirements in memory operations, such as writing or reading, of MLC memories so that an application may write and read a digital data value as an approximate value. Types of MLCs include Flash MLC and MLC Phase Change Memory (PCM) as well as other resistive technologies. Many software applications may not need the accuracy or precision typically used to store and read data values. For example, an application may render an image on a relatively low resolution display and may not need an accurate data value for each pixel. By relaxing the precision or correctness requirements is a memory operation, MLC memories may have increased performance, lifetime, density, and/or energy efficiency.
    Type: Application
    Filed: September 25, 2014
    Publication date: January 8, 2015
    Inventors: Karin Strauss, Douglas C. Burger, Luis Henrique Ceze, Adrian Sampson