Abstract: An asynchronous logic circuit has a plurality of input lines (I) connected both to an n-channel logic block (NL) and to a p-channel logic block (PL) which is inverse with respect thereto (split transistor switch logic), in which, both in response to a rising and to a falling edge of a request signal at a request input (REQ), valid output data can be produced at outputs (OUT1, OUT2) of the asynchronous logic circuit in each case before a signal change at a ready-message output (RDY). Advantages are in particular the low outlay on circuitry and the doubling of the throughput in comparison with a corresponding status-controlled asynchronous logic circuit.

Abstract: A logic circuit for asynchronous circuits, in which logic circuit signals which are present at the input (in) of the logic circuit can be linked both in a first logic block (NL) and also in a second logic block (PL) inverse thereto, and in which logic circuit, at a complete message output (cmpl), a signal can be formed to report valid data at an output (out) of the logic circuit, by a logic link (E), from signals from outputs of both logic blocks. In order to achieve a greater interference resistance and a lower power loss with the simultaneous use of conventional CMOS logic blocks, the first logic section is formed with n-channel transistors and the second logic section is formed with p-channel transistors and the outputs (A1 and A6) of the two logic sections are coupled to one another via transistors (8 and 10).

Abstract: A digital neural network has a plurality of neurons (NR) completely meshed with one another, each of which comprises an evaluation stage having a plurality of evaluators (B) that is equal in number to the plurality of neurons (NR) and each of which comprises a decision stage having a decision unit (E). An adjustment information (INF.sub.E) that effects a defined pre-adjustment of the decision unit (E) can be supplied to every decision unit (E) by a pre-processing means via an information input. A weighting information (INF.sub.G) can be supplied to every evaluator (B) by a pre-processing means via an individual information input. An output information (INF.sub.A) can be output by every decision unit (E) to a post-processing means via a respective individual information output. The information outputs of the decision units (E) are each connected to an individual processing input of all evaluators (B) allocated to the appertaining decision unit (E).

Abstract: A network architecture for the programmable emulation of large artificial neural networks ANN having digital operation employs a plurality L of neuron units of identical structure, each equipped with m neurons, the inputs (E) thereof being connected to network inputs (E.sub.N) multiplied or branching via individual input registers (REG.sub.E). The outputs (A) of the neuron units are connectable to network outputs (A.sub.N) at different points in time via individual multiplexers (MUX) and individual output registers (REG.sub.A) and the neuron units have individual auxiliary inputs via which signals can be supplied to them that represent weighting values (W) for weighting the appertaining neural connections and represent thresholds (0) for weighting input signals.

Abstract: A carry-select adder composed of blocks, each containing an input adder cell and a number of adder cells of a first and second type. Each block has one input adder cell interconnected to adder cells of the first and second type which are connected in an alternating fashion. The cells are connected to each other via carry lines and block carry lines. The adder cells of the first and second type each have a gate arrangement which utilizes field effect transistors for transfer, pull-up and pull-down transistors. These transistors are not a component part of a combination gate within an adder cell. The gate arrangement significantly increases the processing speed of the carry-select adder.

Abstract: A multi-place ripple-carry adder adapted for CMOS technology incorporates two types of adder cells in which the adder cells of a first type receive two operand inputs and an inverted carry input signal and produce outputs corresponding to a sum signal and a non-inverted carry output signal. The adder cells of the second type accept two operand inputs and produce, as outputs, a sum signal and a non-inverted carry output signal. The gate arrangements of the adder cells of each type are designed so that the capacitance of the carry output is charged through either one transfer transistor acting as a transfer gate, or through a series connection of two transistors of which one transistor acts as a transfer gate. Both binary values can be transmitted as inverted and non-inverted carry output signals without additional threshold voltage losses.

Abstract: An adder cell in which the sum signal and the carry signal are formed with equal speed is provided for employment in "carry-save" adders, wherein the sum signal and the carry signal are separately forwarded to separate inputs of following adder cells. The circuit of the adder cell is designed such that the sum signal as well as the carry signal each have to traverse only two gates, so that the running times of sum signal and carry signal are approximately identical and shorter than the maximum running time of conventional adder cells.

Abstract: An adder cell for a ripple-carry adder, suitable for use in an integrated circuit employing CMOS technology, has a gate arrangement for two input variables and a carry input signal, with outputs for sum and carry signals, in accordance with the signals presented to the inputs. The gate arrangement is arranged so that the charging of the capacitance of the carry output takes place from a supply voltage through two transistor gates, not contained in a combination gate, so that one of the transistor gates may be formed as a driving inverter separate from the time-critical carry-propogation path, and designed with significantly lower impedance than the other transistor gates. Alternatively, a single transistor gate is employed for charging the capacitance of the carry output directly form a supply voltage.

Abstract: A transversal filter has an analog shift register exhibiting a series input and a plurality of parallel outputs which are connected to a summing and/or subtracting circuit. A simple realization of signal weighting circuits assigned to the stages of the shift register is achieved in that n signal weighting devices assigned to a group of n stages are disposed in a signal path which extends from the input of the first stage of the group over all stages thereof and in that the signal weighting devices of the n stages respectively weight according to filter coefficients b.sub.1 -b.sub.n which occur in the system functionH(z)=b.sub.0 .multidot.(1+b.sub.1 .multidot.z(1+b.sub.2 .multidot.z(. . . (1+b.sub.n .multidot.z))))determining the filtered signal, where z represents the delay time per stage for each signal value. The transversal filter of the invention is useful in analog filters of communications technology.

Abstract: A transversal filter with an analog shift register has a plurality of parallel inputs and a serial output at which a filtered signal appears. An object is to provide as simple as possible a realization of the n signal evaluators allocated to the n stages of the shift register. This is achieved by providing the n signal evaluators in a signal path proceeding from the input of the first stage over all n stages, and to evaluate according to evaluation factors b.sub.n through b.sub.1 which occur in the system functionH(z)=b.sub.o .multidot.(1+b.sub.1 z(1+b.sub.2 .multidot.z( . . . 1+b.sub.n .multidot.z)))describing the filtered signal, where z is the delay which the signal values respectively experience when traversing a stage of the shift register. The filter is employed as an analog filter in communication technology.

Abstract: An input stage for a monolithically integrated charge transfer device of the type which generates two complementary charge packets from one input signal, said input stage having at least two transfer gates disposed between a source region in a semiconductor body and an input gate which is charged with the input signal. The two transfer gates in the input stage are connected to clock pulse voltages which operate at one half the clock frequency of the transfer stages covering the transfer channel of the charge transfer device. A particularly low-noise encoding of the input signal into the two complementary charge packets results thereby and the structure is particularly suitable for analog signal processing.

Abstract: The invention relates to an input stage for a charge transfer device (CTD) arrangement which contains a source zone in a semiconductor body, two input electrodes, and a transfer gate, wherein one input gate is connected to a fixed voltage, and the other input gate is supplied with an analog input signal. In input stages of this kind, it is endeavored to evaluate the input signal within the widest possible limits without the need of altering the assigned semiconductor surface. The invention achieves this aim in that the input stage is divided into two input channels which possess different widths and which open into the CTD channel. A positive evaluation of the input signal is carried out via the first input channel, whereas a negative evaluation is carried out via the second input channel. The difference in area between the second input gate electrodes of the two input channels represents a gauge of the evaluation coefficient and can be kept very small.

Abstract: The invention relates to a CTD arrangement comprising an input stage (ETS) which increases each of the input, signal-dependent charge quantities by basic charges (fat zero). In arrangements of this kind, it is endeavored to eliminate the influence of fluctuations in operating voltages upon the d.c. voltage component or d.c. component of the output signal. The invention solves this problem in that a compensation stage (KST) which fully eliminates the added basic charges is inserted into the CTD channel. The sphere of application for the invention includes CTD circuits, and in particular CTD transversal filter circuits.

Abstract: A dynamic element is disclosed which is constructed on a doped semiconductor substrate. A strip-shaped semiconductor region, which is on a surface of the substrate and which is doped opposite to the substrate, is designed as a first selection line, whereas a path which is separated by means of an insulating layer from the substrate, and which runs cross-wise to the strip-shaped region, represents a second selection line. The path is separated from a substrate region which lies next to the strip-shaped region by means of a thin film region of the insulating layer. In the case of memory elements of this type, simple construction and small dimensions are desired. According to the invention, this is achieved in that inside of the strip-shaped region, an island-shaped semiconductor region doped opposite to the strip-shaped region is arranged and which lies close to an interface of the strip-shaped region separating it from the semiconductor region which lies under the thin film region.

Abstract: A CTD transversal filter is disclosed which comprises a CTD arrangement with parallel inputs and evaluation circuits. The evaluation coefficients are set up in digital fashion by means of comparator-controlled input sequences of signal-dependent quantities of charge. High value coefficients may be established without the need to reduce a lower frequency transmission limit. With the invention, the transfer electrodes of the CTD are not supplied with the normal clock voltages but with the output voltages of a shift register in which circulates an item of logic information which forwards the input charges individually and consecutively by one electrode spacing. The application of this "electrode-per-bit" operation results in a considerable increase in the times for the individual input sequences. The invention is useful in programmable frequency filters.

Abstract: A dynamic storage element has an electrically insulating layer carried on a substrate of semiconductor material. A conductor path, provided with a terminal, is arranged on the electrically insulating layer, and first and second zones, doped oppositely to the substrate, are provided on the surface of the substrate. The zones are spaced from one another. In that region of the substrate between the zones the substrate is more highly doped with dopants of the same type as those contained in the substrate and the conductor path extends above the highly doped region.

Abstract: A transversal filter utilizes a charge transfer device (CTD) shift register having parallel inputs and evaluation circuits assigned to those inputs. The evaluation circuits which form evaluation coefficients by reading-in signal-dependent amounts of charges. The charges are summed in the shift register and the charges successively reaching the output level are read out in series in order to form the filtered output signal. An electric coefficient setting is provided which guarantees a large relative adjustment range having a small requirement for semiconductor surface. The evaluation circuits have separately actuated source zones or additional source zones which are arranged in pairs on opposite sides of the CTD transfer channel, or which are provided with gate oxide and field oxide areas arranged beneath a transfer gate between the evaluation circuits and the shift register. A transversal filter constructed according to the invention is suitable for use as an electrically programmable frequency filter.

Abstract: A regenerator circuit for charge coupled devices removes charges produced by leakage currents along the shift channel of the charge coupled device. The regenerator circuit may also remove echo signals which develop in the shift channel. For removing charge produced leakage currents at given intervals along a shift channel of a substrate, an electrode is provided adjacent an electrode of a shift element and at a side of the shift channel. A diffusion zone doped oppositely to the substrate is arranged at the side of this shift element electrode. An electrode which follows the electrode of the shift element in the direction of charge shift has a separate terminal. For removing echo signals developed in the shift channel, a further electrode is arranged between electrodes of oppositely facing shift elements in a CCD loop. A shift element electrode which follows one of the shift element electrodes on either side of the further electrode has a separate terminal.

Abstract: A transversal filter is disclosed in which the stages of an analog charge transfer device shift register, integrated on a doped semiconductor substrate, are provided with parallel inputs and evaluation circuits preconnected to the parallel inputs. The evaluation circuits respectively exhibit an area doped opposite to the substrate, a first input gate and a second input gate and a transfer gate, whereby the transfer gate is arranged immediately next to the transfer channel of the charge transfer device shift register. The one input gate is connected to an input signal, the other input gate is connected to a constant direct voltage, the oppositely doped area is connected to a first clock pulse voltage and the transfer gate is connected with a second clock pulse voltage. The output signal can be tapped at an output of the charge transfer device shift register. Comparators are provided having first inputs connected with a counter which is loaded with clock pulses and second inputs connected with digital memories.

Abstract: In the illustrated embodiments, the space required for a transversal filter with a given number of evaluation factors is reduced by providing valuator circuits embodying such factors as inputs to each successive capacitor element of a charge shifting device. In one mode of operation the signal to be filtered is sampled via the valuator circuits on each charge shift cycle while readout from the series output occurs on alternate cycles. Since the readout scanning frequency is a submultiple of the input sampling frequency, the filter is well suited as a low-pass filter.