Abstract: A biometric classification system includes a biometric capture system that captures a biometric identifier. A classifier includes a plurality of group classifiers. Each group classifier in the plurality of classifiers includes a group discriminator that determines, based on the captured biometric identifier, whether the biometric identifier belongs to a group of persons associated with the group discriminator, and includes a plurality of object discriminators. Each object discriminator is associated with a single person within the group of persons. The group discriminator determines whether the biometric identifier belongs to the group of persons. The object discriminator determines whether the biometric identifier belongs to the single person associated with the object discriminator.

Abstract: A biometric classification system includes a biometric capture system that captures a biometric identifier. A classifier includes a plurality of group classifiers. Each group classifier in the plurality of classifiers includes a group discriminator that determines, based on the captured biometric identifier, whether the biometric identifier belongs to a group of persons associated with the group discriminator, and includes a plurality of object discriminators. Each object discriminator is associated with a single person within the group of persons. The group discriminator determines whether the biometric identifier belongs to the group of persons. The object discriminator determines whether the biometric identifier belongs to the single person associated with the object discriminator.

Abstract: An improved data packet design that can be used in a variety of data communication standards used in smart meter systems is disclosed. In an embodiment a smart meter system that comprises of a local server, a coordinator and a plurality of smart meters in the many-to-one data communication system configuration. The smart meter uses a variety of types of radio frequency data packets. The data packets contain the commands, parameters, and data for system control and data transmission. The data packet designs are disclosed for a route discovery command, a get parameter command, a set parameter command, a get data command, a reset command, a relay command, a start command, and a calibration command that are used in the smart meter system.

Abstract: An improved data packet design that can be used in a variety of data communication standards used in smart meter systems is disclosed. In an embodiment a smart meter system that comprises of a local server, a coordinator and a plurality of smart meters in the many-to-one data communication system configuration. The smart meter uses a variety of types of radio frequency data packets. The data packets contain the commands, parameters, and data for system control and data transmission. The data packet designs are disclosed for a route discovery command, a get parameter command, a set parameter command, a get data command, a reset command, a relay command, a start command, and a calibration command that are used in the smart meter system.

Abstract: An improved data packet design that can be used in a variety of data communication standards used in smart meter systems is disclosed. In an embodiment a smart meter system that comprises of a local server, a coordinator and a plurality of smart meters in the many-to-one data communication system configuration. The smart meter uses a variety of types of radio frequency data packets. The data packets contain the commands, parameters, and data for system control and data transmission. The data packet designs are disclosed for a route discovery command, a get parameter command, a set parameter command, a get data command, a reset command, a relay command, a start command, and a calibration command that are used in the smart meter system.

Abstract: A smart meter system architecture comprises of a local server, a coordinator, and a plurality of smart meters in a one-to-many data communication system configuration is disclosed. The invention discloses the architecture for a coordinator-server interface control register, data registers, routing table, non-volatile memory, parameter register, non-interruptible battery backup subsystem, and a low-power energy calculation and calibration method for resistive loads.

Abstract: A transformer-less method and system for voltage and current sensing using voltage drops across resistors is disclosed. Using optically coupled isolators, the sensed voltages in the high voltage power lines are optically coupled and electrically isolated to the low voltage circuits. The circuit designs for voltage and current sensing's and electrical isolation are disclosed.

Abstract: A smart meter system architecture comprises of a local server, a coordinator, and a plurality of smart meters in a one-to-many data communication system configuration is disclosed. The invention discloses the architecture for a coordinator-server interface control register, data registers, routing table, non-volatile memory, parameter register, non-interruptible battery backup subsystem, and a low-power energy calculation and calibration method for resistive loads.

Abstract: An improved data packet design that can be used in a variety of data communication standards used in smart meter systems is disclosed. In an embodiment a smart meter system that comprises of a local server, a coordinator and a plurality of smart meters in the many-to-one data communication system configuration. The smart meter uses a variety of types of radio frequency data packets. The data packets contain the commands, parameters, and data for system control and data transmission. The data packet designs are disclosed for a route discovery command, a get parameter command, a set parameter command, a get data command, a reset command, a relay command, a start command, and a calibration command that are used in the smart meter system.

Abstract: A transformer-less method and system for voltage and current sensing using voltage drops across resistors is disclosed. Using optically coupled isolators, the sensed voltages in the high voltage power lines are optically coupled and electrically isolated to the low voltage circuits. The circuit designs for voltage and current sensing's and electrical isolation are disclosed.

Abstract: A transformer-less method and system for voltage and current sensing using voltage drops across resistors is disclosed. Using optically coupled isolators, the sensed voltages in the high voltage power lines are optically coupled and electrically isolated to the low voltage circuits. The circuit designs for voltage and current sensing's and electrical isolation are disclosed.

Abstract: A nonvolatile memory architecture (10) contains a plurality of memory arrays (12) formed by a plurality of floating gate memory cells and supports a 1.times. and 2.times. architecture. The nonvolatile memory design contains high voltage row decoders (16), low voltage row decoders (18), data multiplexors (24) and low voltage control circuitry (22). The nonvolatile memory architecture (10) features a pipelined scheme with a 100 MHz operation. Data multiplexers (24) and sense amplifier circuitry (26) with a master/slave portion increase the data access rate.

Abstract: A nonvolatile memory architecture (10) contains a plurality of memory arrays (12) formed by a plurality of floating gate memory cells and supports a 1X and 2X architecture. The nonvolatile memory design contains high voltage row decoders (16), low voltage row decoders (18), data multiplexors (24) and low voltage control circuitry (22). The nonvolatile memory architecture (10) features a pipelined scheme with a 100 MHz operation. Data multiplexers (24) and sense amplifier circuitry (26) with a master/slave portion increase the data access rate.

Abstract: A modified Widlar current source (74) includes a first transistor (84) having a collector providing a first terminal of the current source (74), a base, and an emitter connected through a first resistor (85) to a second terminal of the current source (74). A second transistor (82) has a collector connected to a power supply voltage terminal through a second resistor (81) and to the base of the first transistor (84), a base connected to the collector thereof, and an emitter connected to the second terminal of the current source (74) through a third resistor (83). A switching portion (80) selectively reduces a resistance between the power supply voltage terminal and the collector of the second transistor (82) in response to a control signal. Thus, current is selectively reduced, such as during a non-switching time of a logic circuit (70).

Abstract: A memory (20) for performing read cycles and write cycles has memory cells (30) located at intersections of word lines (32) and bit line pairs (34). A write control circuit (44) receives a write enable signal. The logic state of the write enable signal determines whether memory (20) writes data into, or reads data from, memory (20). Memory (20) includes row address decoding for selecting a word line (32). During a write cycle, a control signal generated by write control circuit (44) and single-sided delay circuit (45) is provided to row predecoder (42). The old row address is latched, and a new address is prevented from selecting a new word line (32) until the write enable signal changes state to begin a read cycle. Controlling word line selection with the write enable signal ensures that bit line equalization occurs before the beginning of a read cycle.

Abstract: A BICMOS memory performs address transition detection on each address signal. A first ECL difference amplifier detects a low-to-high transition with a first input being the address signal, and a second input being the address signal delayed and level-shifted. A second ECL difference amplifier uses a complement of the first and second inputs to detect a high-to-low transition. The outputs of two corresponding ECL difference amplifiers for each address signal are wire-ORed together to form the address transition detection signal, which is delayed for first, second, and third predetermined times to sequentially perform row predecoding, row decoding, and block decoding, respectively. The decoding is performed by logic circuits using modified Widlar current sources, which decrease the current required except during decoding, as indicated by a corresponding address transition detection signal. The saving in current allows faster ECL circuits to be used and decreases peak current on internal power supply lines.

Abstract: An integrated circuit memory with improved di/dt control. The memory stores a plurality of data bits at intersections of word lines and bit line pairs. In response to a change in at least one of a plurality of address signals during a read cycle, first and second precharge signals are asserted, the second precharge signal asserted after the first precharge signal. An output buffer provides a data output signal at a voltage between a logic high and a logic low voltage in response to an assertion of the second precharge signal, and provides said data output signal corresponding to a voltage on an enabled bit line pair in response to a negation of the first precharge signal. Thus, the voltage on the data output signal changes less when the data bit is provided during the data period. The memory thus improves di/dt for a given access time, or conversely, allows reduced access time for a given di/dt.

Abstract: A memory uses address transition detection to reduce power consumption of the output amplification stage. The output amplification stage, which drives an output driver, has a series of stages which are disabled except when there is an address transition. When there is an address transition all of the stages are quickly enabled except the last stage. The last stage has its output clamped to an invalid state when the other stages are first enabled and then is enabled a predetermined time after the other stages are enabled. The output of the last stage is sensed by a detector. After the last stage has been enabled and is providing valid data, the detector detects that the output of the last stage is valid, and the series of stages are all disabled. The output driver latches the data and provides an output. The output stage is thus disabled and thus not wasting power except during the portion of a cycle when there is actual need for amplification.

Abstract: An output buffer in an integrated circuit comprising voltage regulator, a predriver, and an output stage. The integrated circuit comprises a chip and a package and interconnections therebetween. The voltage regulator is coupled to a first power supply voltage terminal and a second power supply voltage terminal, and provides a regulated voltage signal characterized as having a constant voltage substantially independent of fluctuations in voltage between the first power supply voltage terminal and the second power supply voltage terminal. The predriver receives the regulated voltage signal and a data input signal and provides a regulated predriven signal in response to the data signal. The output stage receives the regulated predriven signal and provides an output signal in response thereto. The output signal is driven onto a bonding pad of the device to provide an interconnection point between the chip and the package.

Abstract: A multiple element integrated circuit trench cell having at least one vertical field effect transistor (FET) in a wall of a trench in a semiconductor substrate. The cell further comprises a central load device within the trench which is electrically connected to the vertical FET. The central load device may be an active load device, such as another field effect transistor, or a passive load device, such as a resistor. Additionally, a further FET may be present in another wall of the trench or in a lateral orientation adjacent the trench in the semiconductor surface. Two of these multiple element trench cells may be interconnected in various configurations to form conventional static random access memory (SRAM) cells.