Karl L. Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
Abstract: A semiconductor memory device having a divided word line architecture in which each block of the memory array is divided into half-blocks and the half-blocks of each block are located on different halves of the device separated by the row decoder. A data line bussing scheme cooperates with this unique organization of the memory array to provide for sense amplifier sharing. This feature allows fewer, and larger sense amplifiers for better performance.
Abstract: In a random access memory a write driver develops a full rail write signal which is coupled to the selected bit line pair via transmission gates. The bit lines are thus driven to full rail. This results in a faster rise time on the bit line which is driven to a logic high. With the faster rise time, the selected cell is written into more quickly with the result of a faster write time for the memory.
Abstract: A memory has a memory cells located at intersections of bit line pairs and word lines. During a write mode of the memory, the bit lines are at a maximum voltage separation. For a read to occur following a write, the bit lines must first be equalized. Because of the extent of the voltage separation during a write, equalizing the bit lines can cause a large peak current drain on the power supply. This peak current is reduced by partially charging the bit lines in response to a write to read transition then bringing the bit lines to the final equalization voltage in response to a transition of the row address. The partial charging is ensured of occurring first in the event that the write to read transition occurs simultaneously with a row address transition to ensure a reduced peak current.
March 3, 1986
Date of Patent:
June 14, 1988
Karl L. Wang, Mark D. Bader, Peter H. Voss
Abstract: A memory has a read mode in which data is read from a bit line pair selected by a column address and a write mode in which data is written onto a selected bit line pair. The selected bit line pair is coupled to a data line pair via a column decoder in response to a column address. Upon a transition from the write mode to the read mode the column decoder is disabled from coupling the selected data line to the data line pair for the duration of a column disable pulse. The column disable pulse is generated in response to a write transition pulse or a column transition pulse or both. The column transition pulse is generated in response to a change in the column address. The write transition pulse is generated in response to a write to read transition.
Abstract: A CMOS static RAM, which has P channel transistors formed in a second polysilicon layer, N channel transistors formed in the substrate, and gates of both the N channel and P channel transistors formed in a first polysilicon layers, requires that ohmic contact be made between semiconductor material of differing conductivity type. The first polysilicon layer is N-type, and the second polysilicon layer is P-type. Ohmic contact therebetween is achieved by providing a silicide layer which is between these two layers and in physical contact with both. Ohmic contact between N-type regions in the substrate and the second polysilicon layer is similarly achieved by sandwiching silicide therebetween.