Abstract: A gear-change selector module for a gearshift of a motor vehicle has a movable element and a shift fork having a carrier arm which engages in a recess of the movable element. The recess has two actuating faces which cooperate with carrier faces of the carrier arm. Viewed in a section running through the centre axis of the movable element and the centre axis of the recess, the actuating faces are each convex in a first portion extending from the centre axis in the direction of the outside of the movable element. Furthermore, viewed in a section running through the centre axis of the movable element and the centre axis of the recess, the carrier faces each extend in a first portion from radially outside the movable element up to the centre axis of the movable element, and in a second portion from the centre axis in the direction of the free end of the carrier arm. The carrier faces are convex in the second portion.

Abstract: Integrated transistor and method for the production is disclosed. An explanation is given of, inter alia, a transistor having an electrically insulating isolating trench extending from a main area in the direction of a connection region remote from the main area. Moreover, the transistor contains an auxiliary trench extending from the main area as far as the connection region remote from the main area. The transistor requires a small chip area and has outstanding electrical properties.

Abstract: A field effect transistor (FET) and fabrication method are disclosed. The FET includes a drift region formed in a substrate. A trench adjoins the drift region and contains at least one control region and a connection region. An inversion channel region is isolated from the control region. A portion of the trench extends to the same depth as a second trench that insulates the FET from other components formed in the substrate. Insulating material is disposed between the trench below the control region and the control region. An insulating layer insulates the FET from the substrate. The trench and/or the connection region may extend into the insulating layer or may be isolated from the insulating layer via the drift region.

Abstract: Integrated transistor and method for the production is disclosed. An explanation is given of, inter alia, a transistor having an electrically insulating isolating trench extending from a main area in the direction of a connection region remote from the main area. Moreover, the transistor contains an auxiliary trench extending from the main area as far as the connection region remote from the main area. The transistor requires a small chip area and has outstanding electrical properties.

Abstract: A method for producing an integrated PIN photodiode. The PIN photodiode contains a doped region of a first conduction type near the substrate and a doped region that is remote from the substrate. The doped region that is remote from the substrate has a different construction type than the region near the substrate. In addition, an intermediate region provided that is a range between the doped region remote from the substrate and the doped region near the substrate. The intermediate region is undoped or provided with weak doping.

Abstract: The invention relates to a parking brake, especially for a motor vehicle. Said parking brake (1) comprises a cable traction device in order to actuate the brake and opposite cable deflection by means of at least two deflection rollers (6, 7, 19, 20). The deflection rollers (6, 7, 19, 20) are arranged in such a manner that the connection line can be rotated between the rotational axis of at least two deflection rollers (7, 8, 19, 20) with respect to the drive main axis (18). As a result, a parking brake which is simple to construct and which requires a minimum amount of space is produced. Said parking brake can tighten two brake cables with an essentially equal force in an opposite direction.

Abstract: A field effect transistor (FET) and fabrication method are disclosed. The FET includes a drift region formed in a substrate. A trench adjoins the drift region and contains at least one control region and a connection region. An inversion channel region is isolated from the control region. A portion of the trench extends to the same depth as a second trench that insulates the FET from other components formed in the substrate. Insulating material is disposed between the trench below the control region and the control region. An insulating layer insulates the FET from the substrate. The trench and/or the connection region may extend into the insulating layer or may be isolated from the insulating layer via the drift region.

Abstract: An explanation is given of, inter alia, a method for fabricating an integrated pin photodiode which contains a buried region (20) and a terminal region (32) leading to the buried region (20). This fabrication method enables the pin photodiode (14) to be integrated in a simple manner. Moreover, there is the possibility that process steps for fabricating the pin diode can also be utilized for fabricating shielding wells (22, 56).

Abstract: A capacitor for an integrated circuit with microstructure has a first and a second electrode separated by a dielectric layer. The dielectric layer is produced during the structuring of the first electrodes by an etching process. The dielectric layer comprises a polymer structure which is formed during the etching process, and/or etching products of the electrode metal. The first electrode may be cylindrical and surrounded by a hollow-cylindrical dielectric layer. The capacitor may be integrated in a memory field with a multiplicity of such capacitors.

Abstract: A semiconductor structure includes a base layer of a first conductivity type, a first layer of the first conductivity type arranged on the base layer and having a dopant concentration that is lower than a dopant concentration of the base layer, and a second layer of a second conductivity type being operative with the first layer in order to form a transition between the first conductivity type and the second conductivity type. A course of a dopant profile at the transition between the base layer and the first layer is set such that in an ESD case a space charge region shifted to the transition between the base layer and the first layer reaches into the base layer.

Abstract: A method for the fabrication of a DMOS transistor structure provides the advantage that, through the use of a protective layer, the DMOS transistor structure, which has already been substantially completed, is protected from the adverse effects of further process steps. The DMOS gate electrode is not, as is customary in the prior art, patterned using a single lithography step, but, rather, the patterning of the DMOS gate electrode is split between two lithography steps. In a first lithography step, substantially only the source region of the DMOS transistor structure is opened. Therefore, the electrode layer that is still present can be used as a mask for the subsequent fabrication of the body region.

Abstract: A semiconductor structure includes a base layer of a first conductivity type, a first layer of the first conductivity type arranged on the base layer and having a dopant concentration that is lower than a dopant concentration of the base layer, and a second layer of a second conductivity type being operative with the first layer in order to form a transition between the first conductivity type and the second conductivity type. A course of a dopant profile at the transition between the base layer and the first layer is set such that in an ESD case a space charge region shifted to the transition between the base layer and the first layer reaches into the base layer.

Abstract: A method for the fabrication of a DMOS transistor structure provides the advantage that, through the use of a protective layer, the DMOS transistor structure, which has already been substantially completed, is protected from the adverse effects of further process steps. The DMOS gate electrode is not, as is customary in the prior art, patterned using a single lithography step, but, rather, the patterning of the DMOS gate electrode is split between two lithography steps. In a first lithography step, substantially only the source region of the DMOS transistor structure is opened. Therefore, the electrode layer that is still present can be used as a mask for the subsequent fabrication of the body region.

Abstract: A membrane of the micromechanical semiconductor configuration is formed within a cavity. The membrane is formed by a crystalline layer within the substrate or within an epitaxial sequence of layers of the semiconductor configuration arranged on a substrate. The membrane is laid at the edge region on a support and is covered over by a covering layer supported on a counter-support. The support and the counter-support have a different etch rate from the membrane. Wet-chemical etching of the layer sequence with an etchant that is selective to the material of the membrane thus leads to the formation of a cavity around the membrane. Preferably, the layers are formed of differently doped materials.

Abstract: The invention defines a method for fabricating a semiconductor insulation layer: A semiconductor substrate is first provided; an insulation layer is applied by way of region-by-region or whole-area application to the semiconductor substrate; impurity ions are selectively implanted into at least one predetermined zone of the insulation layer; then the insulation layer is selectively etched, and the insulation layer is thereby patterned in accordance with the zone or zones of the selectively implanted impurity ions.

Abstract: A fusible link in an integrated semiconductor circuit and a process for producing the fusible link contemplate the disposition of a fusible link, which is constructed with a cross-sectional constriction as a desired fusing point for its conductor track, in a void. A surface of the void and/or a bare conductor track can be covered with a protection layer, to prevent corrosion. The advantages of such a fusible link are a lower ignition energy and increased reliability. The fusible link may be used as a memory element of a PROM.

Abstract: The invention defines a method for fabricating a semiconductor insulation layer: A semiconductor substrate is first provided; an insulation layer is applied by way of region-by-region or whole-area application to the semiconductor substrate; impurity ions are selectively implanted into at least one predetermined zone of the insulation layer; then the insulation layer is selectively etched, and the insulation layer is thereby patterned in accordance with the zone or zones of the selectively implanted impurity ions.

Abstract: The invention defines a method for fabricating a semiconductor insulation layer: A semiconductor substrate is first provided; an insulation layer is applied by way of region-by-region or whole-area application to the semiconductor substrate; impurity ions are selectively implanted into at least one predetermined zone of the insulation layer; then the insulation layer is selectively etched, and the insulation layer is thereby patterned in accordance with the zone or zones of the selectively implanted impurity ions. Likewise, the present invention provides a method for fabricating a semiconductor component containing this semiconductor insulation layer.

Abstract: A fusible link in an integrated semiconductor circuit and a process for producing the fusible link contemplate the disposition of a fusible link, which is constructed with a cross-sectional constriction as a desired fusing point for its conductor track, in a void. A surface of the void and/or a bare conductor track can be covered with a protection layer, to prevent corrosion. The advantages of such a fusible link are a lower ignition energy and increased reliability. The fusible link may be used as a memory element of a PROM.

Abstract: A method for producing complementary MOS and bipolar transistors on the same semiconductor wafer, includes producing buried zones of differing conductivity, producing n- and p-doped wells for corresponding transistors, and producing field oxide regions and insulated gate electrodes of the MOS transistors. After production of the field oxide regions, highly doped n-regions extending from a surface of the semiconductor wafer to a buried n-doped zone are produced with a first mask for producing a collector zone of an npn transistor and a base zone of a pnp transistor. After the production of the insulated gate electrodes, a first silicon layer is applied over the entire surface and doped with p-atoms. An auxiliary layer is applied on the first silicon layer over the entire surface. The auxiliary layer and the first silicon layer are structured with a second mask.