Abstract: In a method for producing a gate structure for a MOS transistor, first, a layer sequence of oxide layer, auxiliary layer and masking layer is generated on a substrate, wherein the auxiliary layer and the masking layer are patterned to determine an edge separating an area of the oxide layer covered by these layers from an exposed area thereof. Afterwards, an oxidation is performed to generate an oxide ramp in the area of the edge. Then, the auxiliary layer is partly removed to generate a hollow space of predetermined length between the oxide layer and the masking layer. A gate electrode material is introduced into the hollow space for generating a gate electrode.

Abstract: A semiconductor structure includes a base layer of a first conductivity type, a first layer of the first conductivity type arranged on the base layer and having a dopant concentration that is lower than a dopant concentration of the base layer, and a second layer of a second conductivity type being operative with the first layer in order to form a transition between the first conductivity type and the second conductivity type. A course of a dopant profile at the transition between the base layer and the first layer is set such that in an ESD case a space charge region shifted to the transition between the base layer and the first layer reaches into the base layer.

Abstract: A method for the fabrication of a DMOS transistor structure provides the advantage that, through the use of a protective layer, the DMOS transistor structure, which has already been substantially completed, is protected from the adverse effects of further process steps. The DMOS gate electrode is not, as is customary in the prior art, patterned using a single lithography step, but, rather, the patterning of the DMOS gate electrode is split between two lithography steps. In a first lithography step, substantially only the source region of the DMOS transistor structure is opened. Therefore, the electrode layer that is still present can be used as a mask for the subsequent fabrication of the body region.

Abstract: In a method for producing a gate structure for a MOS transistor, first, a layer sequence of oxide layer, auxiliary layer and masking layer is generated on a substrate, wherein the auxiliary layer and the masking layer are patterned to determine an edge separating an area of the oxide layer covered by these layers from an exposed area thereof. Afterwards, an oxidation is performed to generate an oxide ramp in the area of the edge. Then, the auxiliary layer is partly removed to generate a hollow space of predetermined length between the oxide layer and the masking layer. A gate electrode material is introduced into the hollow space for generating a gate electrode.

Abstract: In a securing method for securing an object against unauthorized use, an interrogation unit (1) is used to transmit an interrogation signal (s) and to test whether a response unit (2), which is to be carried by and on an authorized user, responds to the interrogation signal with a response signal (s) that contains as information a code authorized for desecuring a security device (3). If that is the case, the security device is desecured. The securing method is, however, ineffective, if unauthorized persons establish a radio link via relay stations between the interrogation unit (1) and the response unit (2), and via this radio link provide the code authorized for the desecuring to the interrogation unit (1) without being noticed by the authorized user. The new securing method shall prevent such interventions by unauthorized persons.

Abstract: A membrane of the micromechanical semiconductor configuration is formed within a cavity. The membrane is formed by a crystalline layer within the substrate or within an epitaxial sequence of layers of the semiconductor configuration arranged on a substrate. The membrane is laid at the edge region on a support and is covered over by a covering layer supported on a counter-support. The support and the counter-support have a different etch rate from the membrane. Wet-chemical etching of the layer sequence with an etchant that is selective to the material of the membrane thus leads to the formation of a cavity around the membrane. Preferably, the layers are formed of differently doped materials.

Abstract: The invention defines a method for fabricating a semiconductor insulation layer: A semiconductor substrate is first provided; an insulation layer is applied by way of region-by-region or whole-area application to the semiconductor substrate; impurity ions are selectively implanted into at least one predetermined zone of the insulation layer; then the insulation layer is selectively etched, and the insulation layer is thereby patterned in accordance with the zone or zones of the selectively implanted impurity ions.

Abstract: A microelectronic integrated sensor is formed with a cantilever. For the purpose of ensuring a system which is especially invulnerable to mechanical strains during production, the cantilever is placed freely movably on a support, and motion limiters are provided on the edge. The invention also provides for the formation of nitride pillars for supporting the upper layers, in order to further increase the stability. A corresponding production process for producing the sensor is disclosed as well.

Abstract: A fusible link in an integrated semiconductor circuit and a process for producing the fusible link contemplate the disposition of a fusible link, which is constructed with a cross-sectional constriction as a desired fusing point for its conductor track, in a void. A surface of the void and/or a bare conductor track can be covered with a protection layer, to prevent corrosion. The advantages of such a fusible link are a lower ignition energy and increased reliability. The fusible link may be used as a memory element of a PROM.

Abstract: The invention defines a method for fabricating a semiconductor insulation layer: A semiconductor substrate is first provided; an insulation layer is applied by way of region-by-region or whole-area application to the semiconductor substrate; impurity ions are selectively implanted into at least one predetermined zone of the insulation layer; then the insulation layer is selectively etched, and the insulation layer is thereby patterned in accordance with the zone or zones of the selectively implanted impurity ions. Likewise, the present invention provides a method for fabricating a semiconductor component containing this semiconductor insulation layer.

Abstract: A microelectronic integrated sensor is formed with a cantilever. For the purpose of ensuring a system which is especially invulnerable to mechanical strains during production, the cantilever is placed freely movably on a support, and motion limiters are provided on the edge. The invention also provides for the formation of nitride pillars for supporting the upper layers, in order to further increase the stability. A corresponding production process for producing the sensor is disclosed as well.

Abstract: A microelectronic integrate sensor is formed with a cantilever. For the purpose of ensuring a system which is especially invulnerable to mechanical strains during production, the cantilever is placed freely movably on a support, and motion limiters are provided on the edge. The invention also provides for the formation of nitride pillars for supporting the upper layers, in order to further increase the stability. A corresponding production process for producing the sensor is disclosed as well.

Abstract: A method for producing a multiplicity of microelectronic circuits on SOI produces n-CMOS or p-CMOS transistors, NPN transistors or PNP transistors, for instance, through the use of a standardized process, in an especially simple way. All that is required to do so is to adapt the implantations that are performed.

Abstract: A pnp-type bipolar transistor includes a highly dop p-conducting emitter zone, a base zone and a buried n-conducting zone below the emitter zone. An additional p-conducting region is connected to the highly doped emitter zone and is disposed between the highly doped emitter zone and the buried zone. A collector zone includes a highly doped collector connection zone and a p-conducting region reaching from the collector connection zone to the buried zone.

Abstract: A method for producing a multiplicity of microelectronic circuits on SOI uses a standardized process to produce n-CMOS or p-CMOS transistors, NPN-transistors or PNP-transistors, for instance. All that is required to do so is to adapt the implantations that are performed.