Patents by Inventor Karthik Balakrishnan

Karthik Balakrishnan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250102416
    Abstract: Disclosed herein is a system to detect and characterize individual particles and cells using at least either optic or electric detection as the particle or cell flows through a microfluidic channel. The system also provides for sorting particles and cells or isolating individual particles and cells.
    Type: Application
    Filed: December 6, 2024
    Publication date: March 27, 2025
    Inventors: Hany Ramez Nassef, Karthik Balakrishnan, Anand Kesavaraju, Vincent Tuminelli, George Anwar
  • Patent number: 12188858
    Abstract: Disclosed herein is a system to detect and characterize individual particles and cells using at least either optic or electric detection as the particle or cell flows through a microfluidic channel. The system also provides for sorting particles and cells or isolating individual particles and cells.
    Type: Grant
    Filed: June 26, 2023
    Date of Patent: January 7, 2025
    Assignee: NODEXUS INC.
    Inventors: Hany Nassef, Karthik Balakrishnan, Anand Kesavaraju, Vincent Tuminelli, George Anwar
  • Publication number: 20240363412
    Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with a rectangular laser spot-based laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.
    Type: Application
    Filed: April 28, 2023
    Publication date: October 31, 2024
    Inventors: Karthik Balakrishnan, Zavier Tan, Praveen Choragudi, Ananth Jupudi
  • Patent number: 12086264
    Abstract: Systems and methods are described for providing a risk assessment for a software application based on evidence obtained from one or more sources. In some aspects, security and compliance evidence may be obtained from one or more evidence sources, for an application offered through a service provider, where the evidence sources include operational data from the application executing within a runtime environment provided by the service provider. The obtained evidence may be mapped to risk assessment criteria to generate a risk assessment. In some cases, the risk assessment criteria includes a plurality of attributes of the application, with the attributes indicating potential vulnerabilities of the application. A representation of the risk assessment may be generated across at least some of the attributes based on the risk assessment comparison. The risk assessment representation may then be updated based on monitoring of the security and compliance evidence for the application.
    Type: Grant
    Filed: November 26, 2021
    Date of Patent: September 10, 2024
    Assignee: Amazon Technologies, Inc.
    Inventors: Sai Vignesh Vaidyam Anandan, Phillip Simpson, Madhu Preetha Chandrasekaran, Jeremy Jose Elie Hanoun, Karthik Balakrishnan
  • Publication number: 20240254425
    Abstract: Systems and methods for rapid detection and sorting of target particles based on specific characteristics are provided. Optical, electrical, or other detection of the target characteristic in a target particle in a microfluidic sample flow can be used to identify that target particle which can then trigger accurate downstream diversion and isolation of the target particle from the sample flow.
    Type: Application
    Filed: January 17, 2024
    Publication date: August 1, 2024
    Inventors: Hany Nassef, Anand Kesavaraju, Karthik Balakrishnan, Zhiliang Wan
  • Patent number: 12041856
    Abstract: Devices, systems, methods, and/or computer-implemented methods that can facilitate a qubit device comprising a superconducting circuit provided on an encapsulated vacuum cavity are provided. According to an embodiment, a device can comprise a substrate having an encapsulated vacuum cavity provided on the substrate. The device can further comprise a superconducting circuit provided on the encapsulated vacuum cavity.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: July 16, 2024
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Isaac Lauer, Karthik Balakrishnan, Jeffrey Sleight, David James Frank
  • Publication number: 20240127097
    Abstract: Methods and systems for mitigating the effects of defects in a quantum processor are provided. A mitigation system uses an iterative process of applying light pulses and examining qubit relaxation times to eliminate or minimize two-level system (TLS) interaction with qubits. The system applies a first light pulse to illuminate a quantum processor having one or more qubits. The system receives qubit relaxation times that are measured at different electric field frequencies after applying the first light pulse.
    Type: Application
    Filed: October 13, 2022
    Publication date: April 18, 2024
    Inventors: Abram L. Falk, Martin O. Sandberg, Karthik Balakrishnan, Oliver Dial, Jason S. Orcutt
  • Publication number: 20240127095
    Abstract: Methods and systems for mitigating the effects of defects in a quantum processor are provided. A mitigation system includes a quantum processor comprising a plurality of qubits. The system includes a light emitting source that can be tuned to produce light pulses of different wavelengths. The system includes an array of bandpass filters. Each bandpass filter is aligned with a qubit on the quantum processor and has a unique pass band. The system may include a controller configured to receive a selection of a qubit and to tune the light emitting source to emit a light pulse having a wavelength that falls within a range of a bandpass filter that is aligned with the selected qubit. The light pulse is used to scramble an ensemble of strongly coupled two-level system (TLS) in the processor.
    Type: Application
    Filed: October 13, 2022
    Publication date: April 18, 2024
    Inventors: Karthik Balakrishnan, Abram L. Falk, Martin O. Sandberg, Jason S. Orcutt
  • Publication number: 20240127096
    Abstract: Methods and systems for mitigating the effects of defects in a quantum processor are provided. A mitigation system includes a quantum processor having multiple qubits. The system includes an array of light emitting sources. Each light emitting source is aligned with a qubit on the quantum processor. The system includes a controller configured to receive a selection of a qubit and to enable a light emitting source from the array of light emitting sources to emit light to the selected qubit. The light is use to scramble strongly coupled two-level systems (TLSs) in the quantum processor.
    Type: Application
    Filed: October 13, 2022
    Publication date: April 18, 2024
    Inventors: Martin O. Sandberg, Abram L. Falk, Karthik Balakrishnan, Jason S. Orcutt
  • Publication number: 20240079273
    Abstract: An embodiment disclosed herein includes a method of dicing a wafer comprising a plurality of integrated circuits. In an embodiment, the method comprises forming a mask above the semiconductor wafer, and patterning the mask and the semiconductor wafer with a first laser process. The method may further comprise patterning the mask and the semiconductor wafer with a second laser process, where the second laser process is different than the first laser process. In an embodiment, the method may further comprise etching the semiconductor wafer with a plasma etching process to singulate the integrated circuits.
    Type: Application
    Filed: November 14, 2023
    Publication date: March 7, 2024
    Inventors: Jungrae Park, ZAVIER ZAI YEONG TAN, KARTHIK BALAKRISHNAN, JAMES S. PAPANU, WEI-SHENG LEI
  • Patent number: 11901232
    Abstract: Embodiments of the present disclosure include methods of determining scribing offsets in a hybrid laser scribing and plasma dicing process. In an embodiment, the method comprises forming a mask above a semiconductor wafer. In an embodiment, the semiconductor wafer comprises a plurality of dies separated from each other by streets. In an embodiment, the method further comprises patterning the mask and the semiconductor wafer with a laser scribing process. In an embodiment, the patterning provides openings in the streets. In an embodiment, the method further comprises removing the mask, and measuring scribing offsets of the openings relative to the streets.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: February 13, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Karthik Balakrishnan, Jungrae Park, Zavier Zai Yeong Tan, Sai Abhinand, James S. Papanu
  • Patent number: 11869983
    Abstract: A Junction Field Effect Transistor (JFET) has a source and a drain disposed on a substrate. The source and drain have an S/D doping with an S/D doping type. Two or more channels are electrically connected in parallel between the source and drain and can carry a current between the source and drain. Each of the channels has two or more channel surfaces. The channel has the same channel doping type as the S/D doping type. A first gate is in direct contact with one of the channel surfaces. One or more second gates is in direct contact with a respective second channel surface. The gates are doped with a gate doping that has a gate doping type opposite of the channel doping type. A p-n junction (junction gate) is formed where the gates and channel surfaces are in direct contact. The first and second gates are electrically connected so a voltage applied to the first and second gates creates at least two depletion regions in each of the channels.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: January 9, 2024
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Bahman Hekmatshoartabari, Karthik Balakrishnan
  • Patent number: 11854888
    Abstract: An embodiment disclosed herein includes a method of dicing a wafer comprising a plurality of integrated circuits. In an embodiment, the method comprises forming a mask above the semiconductor wafer, and patterning the mask and the semiconductor wafer with a first laser process. The method may further comprise patterning the mask and the semiconductor wafer with a second laser process, where the second laser process is different than the first laser process. In an embodiment, the method may further comprise etching the semiconductor wafer with a plasma etching process to singulate the integrated circuits.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: December 26, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Jungrae Park, Zavier Zai Yeong Tan, Karthik Balakrishnan, James S. Papanu, Wei-Sheng Lei
  • Publication number: 20230382448
    Abstract: A steer by wire system includes at least a steering wheel actuator for operating steering wheel and steering column. The steering wheel actuates the steering wheel actuator by way of a brushless DC motor. The steering wheel actuator adjusts the steering column in a tilt direction by way of a first brushed DC motor and in a telescopic direction by way of a second brushed DC motor. The first brushed DC motor and the second brushed DC motor are configured to operate via two separate H bridges having a shared arm of switches. The brushless DC motor is configured to operate with two three-phase H bridges of which one three-phase H bridge is the network of switches of the first brushed DC motor and the second brushed DC motor.
    Type: Application
    Filed: May 27, 2023
    Publication date: November 30, 2023
    Inventors: Karthik Balakrishnan, Selvaraj Sharath Kumar
  • Publication number: 20230358665
    Abstract: Disclosed herein is a system to detect and characterize individual particles and cells using at least either optic or electric detection as the particle or cell flows through a microfluidic channel. The system also provides for sorting particles and cells or isolating individual particles and cells.
    Type: Application
    Filed: June 26, 2023
    Publication date: November 9, 2023
    Inventors: Hany Nassef, Karthik Balakrishnan, Anand Kesavaraju, Vincent Tuminelli, George Anwar
  • Patent number: 11733152
    Abstract: Disclosed herein is a system to detect and characterize individual particles and cells using at least either optic or electric detection as the particle or cell flows through a microfluidic channel. The system also provides for sorting particles and cells or isolating individual particles and cells.
    Type: Grant
    Filed: May 27, 2022
    Date of Patent: August 22, 2023
    Assignee: NODEXUS INC.
    Inventors: Hany Nassef, Karthik Balakrishnan, Anand Kesavaraju, Vincent Tuminelli, George Anwar
  • Patent number: 11721583
    Abstract: In an embodiment, a semiconductor processing tool for implementing hybrid laser and plasma dicing of a substrate is provided. The semiconductor processing tool comprises a transfer module, where the transfer module comprises a track robot for handling the substrate, and a loadlock attached to the transfer module. In an embodiment, the loadlock comprises a linear transfer system for handling the substrate. In an embodiment, the processing tool further comprises a processing chamber attached to the loadlock, wherein the linear transfer system of the loadlock is configured to insert and remove the substrate from the processing chamber.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: August 8, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Sriskantharajah Thirunavukarasu, Karthik Balakrishnan, Karthik Elumalai, Eng Sheng Peh
  • Patent number: 11697889
    Abstract: A structure including a three-dimensionally stretchable single crystalline semiconductor membrane located on a substrate is provided. The structure is formed by providing a three-dimensional (3D) wavy silicon germanium alloy layer on a silicon handler substrate. A single crystalline semiconductor material membrane is then formed on a physically exposed surface of the 3D wavy silicon germanium alloy layer. A substrate is then formed on a physically exposed surface of the single crystalline semiconductor material membrane. The 3D wavy silicon germanium alloy layer and the silicon handler substrate are thereafter removed providing the structure.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: July 11, 2023
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Karthik Balakrishnan, Stephen W. Bedell, Pouya Hashemi, Bahman Hekmatshoartabari, Keith E. Fogel
  • Patent number: 11686665
    Abstract: Disclosed herein is a system to detect and characterize individual particles and cells using at least either optic or electric detection as the particle or cell flows through a microfluidic channel. The system also provides for sorting particles and cells or isolating individual particles and cells.
    Type: Grant
    Filed: May 27, 2022
    Date of Patent: June 27, 2023
    Assignee: NODEXUS INC.
    Inventors: Hany Nassef, Karthik Balakrishnan, Anand Kesavaraju, Vincent Tuminelli, George Anwar
  • Patent number: RE49954
    Abstract: A method of forming two or more nano-sheet devices with varying electrical gate lengths, including, forming at least two cut-stacks including a plurality of sacrificial release layers and at least one alternating nano-sheet channel layer on a substrate, removing a portion of the plurality of sacrificial release layers to form indentations having an indentation depth in the plurality of sacrificial release layers, and removing a portion of the at least one alternating nano-sheet channel layer to form a recess having a recess depth in the at least one alternating nano-sheet channel layers, where the recess depth is greater than the indentation depth.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: April 30, 2024
    Assignee: TESSERA LLC
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek