Patents by Inventor Karthik Nagarajan

Karthik Nagarajan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220182065
    Abstract: A digital-to-time converter (DTC) converts a digital code into a time delay using a capacitor digital-to-analog converter (CDAC) that functions as a charging capacitor. The DTC includes a switched capacitor voltage-to-current converter for the formation of a charging current (or a discharging current) for charging (or for discharging) the charging capacitor responsive to a triggering clock edge that begins the time delay. A comparator compares a voltage on the charging capacitor to a threshold voltage to determine an end of the time delay.
    Type: Application
    Filed: September 28, 2021
    Publication date: June 9, 2022
    Inventors: Zhengzheng WU, Chao SONG, Karthik NAGARAJAN
  • Publication number: 20220116884
    Abstract: A method of controlling power in a transmission system may include determining a first transmit power of a first transmit path, determining a second transmit power of a second transmit path, and controlling the first transmit path and the second transmit path based on a combination of the first transmit power and the second transmit power. The combination of the first transmit power and the second transmit power may include a sum of the first transmit power and the second transmit power. Controlling the first transmit path and the second transmit path may include determining a first effective power target for the first transmit path based on the first transmit power and the second transmit power, and determining a second effective power target for the second transmit path based on the first transmit power and the second transmit power.
    Type: Application
    Filed: April 5, 2021
    Publication date: April 14, 2022
    Inventors: Pranav DAYAL, Kee-Bong SONG, Hou-Shin CHEN, Sung-En CHIU, Karthik NAGARAJAN
  • Publication number: 20220070823
    Abstract: Methods, systems, and devices for wireless communications are described. A user equipment (UE) may receive, from a base station, a first tracking reference signal configuration and a second tracking reference signal configuration. The first tracking reference signal configuration may include a first set of parameters and the second tracking reference signal configuration may include a second set of parameters. The UE, the base station, or both may identify an indicator for selection from among the first tracking reference signal configuration and the second tracking reference signal configuration. The UE may receive, from the base station and based on the identified indicator for selection, a tracking reference signal in accordance with the first tracking reference signal configuration or the second tracking reference signal configuration.
    Type: Application
    Filed: July 14, 2021
    Publication date: March 3, 2022
    Inventors: Jun Ma, Xiaoxia Zhang, Qiang Wu, Tao Luo, Iyab Issam Sakhnini, Mehmet Izzet Gurelli, Ahmed Abdelaziz Ibrahim Zewail, Jing Sun, Wooseok Nam, Anantha Krishna Karthik Nagarajan, Peter Gaal, Zhifei Fan, Juan Montojo, Sony Akkarakaran, Arumugam Chendamarai Kannan
  • Publication number: 20220007434
    Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment may receive, from a base station, an indication of a time gap value associated with a random access channel (RACH) procedure, wherein the time gap value is based at least in part on a capability of the base station, determine whether a physical RACH (PRACH) occasion associated with the RACH procedure is valid based at least in part on receiving the indication of the time gap value associated with the RACH procedure, and selectively transmit, to the base station, a PRACH transmission in the PRACH occasion based at least in part on determining whether the PRACH occasion is valid. Numerous other aspects are provided.
    Type: Application
    Filed: June 30, 2021
    Publication date: January 6, 2022
    Inventors: Ahmed Abdelaziz Ibrahim Abdelaziz ZEWAIL, Tao LUO, Xiaoxia ZHANG, Qiang WU, Jun MA, Iyab Issam SAKHNINI, Jing SUN, Mehmet Izzet GURELLI, Anantha Krishna Karthik NAGARAJAN, Juan MONTOJO, Peter GAAL
  • Publication number: 20220007421
    Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment may receive, from a base station, a random access configuration indicating synchronization signal block (SSB)-to-random access channel (RACH) occasion mapping information, wherein the SSB-to-RACH occasion mapping information is associated with a first set of RACH occasions and a second set of RACH occasions, select a RACH occasion based at least in part on the SSB-to-RACH occasion mapping information, and transmit, to the base station, a physical RACH communication using the RACH occasion based at least in part on selecting the RACH occasion. Numerous other aspects are provided.
    Type: Application
    Filed: June 30, 2021
    Publication date: January 6, 2022
    Inventors: Ahmed Abdelaziz Ibrahim Abdelaziz ZEWAIL, Xiaoxia ZHANG, Tao LUO, Qiang WU, Jun MA, Iyab Issam SAKHNINI, Mehmet Izzet GURELLI, Anantha Krishna Karthik NAGARAJAN, Jing SUN, Juan MONTOJO, Peter GAAL
  • Publication number: 20220007420
    Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment may receive, from a base station, a random access configuration indicating spreading code information for a set of random access channel (RACH) occasions associated with a RACH procedure, and transmit, to the base station, a physical RACH communication in a RACH occasion, of the set of RACH occasions, using a spreading code, wherein the spreading code is determined based at least in part on the spreading code information. Numerous other aspects are provided.
    Type: Application
    Filed: June 30, 2021
    Publication date: January 6, 2022
    Inventors: Ahmed Abdelaziz Ibrahim Abdelaziz ZEWAIL, Xiaoxia ZHANG, Tao LUO, Qiang WU, Jun MA, Iyab Issam SAKHNINI, Mehmet Izzet GURELLI, Anantha Krishna Karthik NAGARAJAN, Jing SUN, Juan MONTOJO, Peter GAAL
  • Publication number: 20210392593
    Abstract: Methods, systems, and devices for wireless communications are described. A user equipment (UE) may identify a configuration of a set of synchronization signal blocks (SSBs) to be transmitted by a first base station or a second base station. In some cases, the UE may be served by the first base station and the UE may receive, from the first base station or the second base station, a message indicating that a transmission of at least one SSB of the set of SSBs is canceled and indicating resources for a signal (e.g., a reference signal, alternative SSB transmission) to be transmitted by the first base station or the second base station as an alternative to the canceled at least one SSB. The UE may receive, based on the received message from the first base station or the second base station, the signal using the indicated resources.
    Type: Application
    Filed: June 14, 2021
    Publication date: December 16, 2021
    Inventors: Anantha Krishna Karthik Nagarajan, Jun Ma, Tao Luo, Peter Gaal, Qiang Wu, Xiaoxia Zhang, Jing Sun, Mehmet Izzet Gurelli, Iyab Issam Sakhnini, Ahmed Abdelaziz Ibrahim Abdelaziz Zewail, Juan Montojo, Sungwoo Park
  • Patent number: 11177819
    Abstract: A digital-to-time converter (DTC) converts a digital code into a time delay using a capacitor digital-to-analog converter (CDAC) that functions as a charging capacitor. The DTC includes a switched capacitor voltage-to-current converter for the formation of a charging current (or a discharging current) for charging (or for discharging) the charging capacitor responsive to a triggering clock edge that begins the time delay. A comparator compares a voltage on the charging capacitor to a threshold voltage to determine an end of the time delay.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: November 16, 2021
    Assignee: QUALCOMM INCORPORATED
    Inventors: Zhengzheng Wu, Chao Song, Karthik Nagarajan
  • Publication number: 20210296392
    Abstract: Test structures and alignment marks enable accurate measurements of alignment in the active area of an image sensor device. The alignment marks are formed in the active area replacing pixels near the lithographic shot boundaries of the array. Misalignment across the lithographic shots is assessed through the degree of shifting between the alignment patterns. The alignment marks are located in a pixel location of the active area and can measure the actual lithographic shot-to-shot misalignment in the active area, which can be used to make an accurate lithographic alignment. Having such alignment marks allows for a more accurate assessment of the in-line process manufacturing capability as well as a more rapid feedback of in-array drift, which would allow a faster and better control for yield loss.
    Type: Application
    Filed: June 4, 2021
    Publication date: September 23, 2021
    Inventors: Ick-Hwan Ko, Karthik Nagarajan, Byung-Kyu Park, Shawn Michael O'Rourke
  • Patent number: 11004209
    Abstract: Techniques and systems are provided for tracking objects in one or more video frames. For example, a first set of one or more bounding regions are determined for a video frame based on a trained classification network applied to the video frame. The first set of one or more bounding regions are associated with one or more objects in the video frame. One or more blobs can be detected for the video frame. A blob includes pixels of at least a portion of an object in the video frame. A second set of one or more bounding regions are determined for the video frame that are associated with the one or more blobs. A final set of one or more bounding regions is determined for the video frame using the first set of one or more bounding regions and the second set of one or more bounding regions. Object tracking can then be performed for the video frame using the final set of one or more bounding regions.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: May 11, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Ying Chen, Yang Zhou, Karthik Nagarajan, Ning Bi
  • Patent number: 10979068
    Abstract: A digital to analog converter (DAC) includes a plurality of DAC transistor devices having an input side configured to be selectively coupled to a system voltage based on a digital input signal and an output side configured to provide an analog output signal, a plurality of non-DAC transistor devices coupled to the input side of the DAC transistor devices, the non-DAC transistor devices configured as variable resistances, and a control circuit configured to adjust a bias of the non-DAC transistor devices.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: April 13, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Yi-Hung Tseng, Karthik Nagarajan
  • Publication number: 20210091784
    Abstract: A digital to analog converter (DAC) includes a plurality of DAC transistor devices having an input side configured to be selectively coupled to a system voltage based on a digital input signal and an output side configured to provide an analog output signal, a plurality of non-DAC transistor devices coupled to the input side of the DAC transistor devices, the non-DAC transistor devices configured as variable resistances, and a control circuit configured to adjust a bias of the non-DAC transistor devices.
    Type: Application
    Filed: September 20, 2019
    Publication date: March 25, 2021
    Inventors: Yi-Hung TSENG, Karthik NAGARAJAN
  • Patent number: 10958279
    Abstract: Certain aspects of the present disclosure provide apparatus and techniques for digital-to-analog conversion. One example apparatus generally includes a first digital-to-analog converter (DAC) having an input coupled to a digital input node of the apparatus, a second DAC, a digital processor coupled between the digital input node and an input of the second DAC, and a combiner coupled to the first DAC and the second DAC.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: March 23, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Debesh Bhatta, Kevin Jia-Nong Wang, Karthik Nagarajan, John Abcarius, Andrew Weil, Christian Venerus, Jeffrey Mark Hinrichs
  • Publication number: 20210075434
    Abstract: Certain aspects of the present disclosure provide apparatus and techniques for digital-to-analog conversion. One example apparatus generally includes a first digital-to-analog converter (DAC) having an input coupled to a digital input node of the apparatus, a second DAC, a digital processor coupled between the digital input node and an input of the second DAC, and a combiner coupled to the first DAC and the second DAC.
    Type: Application
    Filed: September 6, 2019
    Publication date: March 11, 2021
    Inventors: Debesh BHATTA, Kevin Jia-Nong WANG, Karthik NAGARAJAN, John ABCARIUS, Andrew WEIL, Christian VENERUS, Jeffrey Mark HINRICHS
  • Publication number: 20190304102
    Abstract: Techniques and systems are provided for classifying objects in one or more video frames. An object tracker associated with an object in a current video frame can be selected for object classification. Object classification can be determined to be performed in a next video frame (instead of the current video frame) for the object associated with the selected tracker. An image patch to use for the object classification can be obtained from the next video frame. The image patch can be based on a first bounding region associated with the object tracker in the current video frame, can be based on a second bounding region associated with the tracker in the next video frame, or can be based on both the first and second bounding regions. The object classification can be performed for the object associated with the selected object tracker using the image patch from the next video frame.
    Type: Application
    Filed: March 1, 2019
    Publication date: October 3, 2019
    Inventors: Ying CHEN, Songan MAO, Yang ZHOU, Karthik NAGARAJAN
  • Patent number: 10411718
    Abstract: A method and apparatus for reducing the amount of jitter in a signal are disclosed. In one embodiment a feed-forward loop compares the edges of a reference clock and an input signal, converts a time difference of the compared edges into a voltage signal, and controls a time delay in a voltage controlled delay line in order to reduce or eliminate jitter.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: September 10, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Karthik Nagarajan, Chenling Huang, Debesh Bhatta
  • Publication number: 20190130583
    Abstract: Techniques and systems are provided for tracking objects in a sequence of video frames. For example, an object tracker maintained for the sequence of video frames is identified. An object tracked by the object tracker is detected based on an application of an object detector to at least one key frame in the sequence of video frames. The object detector can include a complex object detector. A status of the object tracker can be updated to a still status in a current video frame of the sequence of video frames. A tracker having the still status is associated with an object that is static in one or more video frames of the sequence of video frames. The object can be tracked in the current video frame using the object tracker based on the status of the object tracker being updated to the still status in the current video frame.
    Type: Application
    Filed: October 26, 2018
    Publication date: May 2, 2019
    Inventors: Ying CHEN, Yang ZHOU, Karthik NAGARAJAN
  • Publication number: 20190130580
    Abstract: Techniques and systems are provided for tracking objects in one or more video frames. For example, a first set of one or more bounding regions are determined for a video frame based on a trained classification network applied to the video frame. The first set of one or more bounding regions are associated with one or more objects in the video frame. One or more blobs can be detected for the video frame. A blob includes pixels of at least a portion of an object in the video frame. A second set of one or more bounding regions are determined for the video frame that are associated with the one or more blobs. A final set of one or more bounding regions is determined for the video frame using the first set of one or more bounding regions and the second set of one or more bounding regions. Object tracking can then be performed for the video frame using the final set of one or more bounding regions.
    Type: Application
    Filed: October 11, 2018
    Publication date: May 2, 2019
    Inventors: Ying CHEN, Yang ZHOU, Karthik NAGARAJAN, Ning BI
  • Publication number: 20190097640
    Abstract: A method and apparatus for reducing the amount of jitter in a signal are disclosed. In one embodiment a feed-forward loop compares the edges of a reference clock and an input signal, converts a time difference of the compared edges into a voltage signal, and controls a time delay in a voltage controlled delay line in order to reduce or eliminate jitter.
    Type: Application
    Filed: September 25, 2017
    Publication date: March 28, 2019
    Inventors: Karthik Nagarajan, Chenling Huang, Debesh Bhatta
  • Patent number: 10147718
    Abstract: An ESD circuit includes a first metal oxide channel device having a drain coupled to a first node, a source coupled to a second node, and a gate coupled to the first node; a second metal oxide channel device having a source coupled to the first node, a drain coupled to the second node, and a gate coupled to the second node; a first capacitor coupled between the first and second nodes proximate to the first metal oxide channel device; and a second capacitor coupled between the first and second nodes proximate to the second metal oxide channel device. The ESD circuit can further include a third capacitor coupled between the first and second nodes proximate to the first capacitor. The ESD circuit can further include a fourth capacitor coupled between the first and second nodes proximate to the second capacitor.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: December 4, 2018
    Assignee: DPIX, LLC
    Inventors: Byung-Kyu Park, Karthik Nagarajan, Jungwon Park, Yang-Wen Chen, Ick-Hwan Ko