Abstract: A system includes a shift register to store data samples, where the shift register includes a cell under test (CUT), a left guard cell, a right guard cell, a left window, and a right window. The system includes two sets of comparators to compare incoming data samples with data samples in the left window and the right window to compute ranks of the incoming data samples. The system includes a sorted index array to store a rank of the data samples in the shift register. The system includes a selector to select a Kth smallest index from the sorted index array and its corresponding data sample from the shift register. The system includes a target comparator, where the first comparator input receives a data sample from the CUT and the second comparator input receives a Kth smallest data sample, and the comparator output indicates a CFAR target detection.

Abstract: A radar device is provided that includes a timing control component operable to generate, for each chirp of a sequence of chirps according to a set of chirp configuration parameters and a chirp profile for the chirp, chirp control signals to cause the radar device to transmit the chirp, the timing control component having chirp configuration parameter inputs, chirp profile parameter inputs, a chirp address output, and chirp control signal outputs, a chirp configuration storage component having chirp configuration parameter outputs coupled to corresponding inputs of the configuration parameter inputs of the timing control component, a chirp profile address output, and a chirp address input coupled to the chirp address output, and a chirp profile storage component having chirp profile parameter outputs coupled to the chirp profile parameter inputs of the timing control component; and a chirp profile address input coupled to the chirp profile address output.

Abstract: A system includes a hardware accelerator configured to perform a two-dimensional (2D) fast Fourier transform (FFT) on an M×N element array. The hardware accelerator has log2 M×N pipeline stages including an initial group of log2 M stages and a final group of log2 N stages. Each stage includes a butterfly unit, a FIFO buffer coupled to the butterfly unit, and a multiplier coupled to the butterfly unit and to an associated twiddle factor table. The hardware accelerator also includes butterfly control logic to provide elements of the M×N element array to the initial group of stages in an N direction of the array, and twiddle factor addressing logic to, for the twiddle factor tables of the initial group of stages, apply an indexed entry of the twiddle factor table to the associated multiplier. The indexed entry begins as a first entry and advances by N entries after every N cycles.

Abstract: A system includes a memory configured to store a two-dimensional data structure that includes radar data arranged such that radar data of a first transmitter is separated from radar data of a second transmitter by a Doppler offset in the two-dimensional data structure. The system also includes a data fetch mechanism that includes a lookup table (LUT) applied on either of two dimensions. The lookup table is configured to store a data fetch location in the two-dimensional data structure, where the data fetch location indicates a location from which to fetch a subset of the radar data from the two-dimensional data structure and the data fetch mechanism is configured to fetch the subset of the radar data from the two-dimensional data structure based on the LUT. The system includes a processor configured to perform a fast Fourier transform (FFT) on the fetched subset of the radar data.

Abstract: An example method may include receiving, at a device, a first frame over a wireless network and constructing a preliminary data portion of a second frame. The second frame may be configured for transmission over the wireless network. The method may also include in response to the receiving of the first frame at the device, beginning transmission of a header portion of the second frame over the wireless network and after the beginning transmission of the header portion of the second frame, constructing, based on the preliminary data portion, a finalized data portion of the second frame for transmission over the wireless network.

Abstract: A radar device is provided that includes a timing control component operable to generate, for each chirp of a sequence of chirps according to a set of chirp configuration parameters and a chirp profile for the chirp, chirp control signals to cause the radar device to transmit the chirp, the timing control component having chirp configuration parameter inputs, chirp profile parameter inputs, a chirp address output, and chirp control signal outputs, a chirp configuration storage component having chirp configuration parameter outputs coupled to corresponding inputs of the configuration parameter inputs of the timing control component, a chirp profile address output, and a chirp address input coupled to the chirp address output, and a chirp profile storage component having chirp profile parameter outputs coupled to the chirp profile parameter inputs of the timing control component; and a chirp profile address input coupled to the chirp profile address output.

Abstract: A FMCW radar system with a built-in self-test (BIST) system for monitoring includes a receiver, a transmitter, and a frequency synthesizer. A FMCW chirp timing engine controls timing of operations at least one radar component. The BIST system includes at least one switchable coupling for coupling a first plurality of different analog signals including from a first plurality of selected nodes in the receiver or transmitter that are all coupled to a second number of monitor analog-to-digital converters (ADCs). The second number is less than (<) the first plurality of different analog signals. The BIST system includes a monitor timing engine and controller operating synchronously with the chirp timing engine, that includes a software configurable monitoring architecture for generating control signals including for selecting using the switchable coupling which analog signal to forward to the monitor ADC and when the monitor ADC samples the analog signals.

Abstract: Methods for monitoring of performance parameters of one or more receive channels and/or one or more transmit channels of a radar system-on-a-chip (SOC) are provided. The radar SOC may include a loopback path coupling at least one transmit channel to at least one receive channel to provide a test signal from the at least one transmit channel to the at least one receive channel when the radar SOC is operated in test mode. In some embodiments, the loopback path includes a combiner coupled to each of one or more transmit channels, a splitter coupled to each of one or more receive channels, and a single wire coupling an output of the combiner to an input of the splitter.

Abstract: A system includes a hardware accelerator configured to perform a two-dimensional (2D) fast Fourier transform (FFT) on an M×N element array. The hardware accelerator has log2 M×N pipeline stages including an initial group of log2 M stages and a final group of log2 N stages. Each stage includes a butterfly unit, a FIFO buffer coupled to the butterfly unit, and a multiplier coupled to the butterfly unit and to an associated twiddle factor table. The hardware accelerator also includes butterfly control logic to provide elements of the M×N element array to the initial group of stages in an N direction of the array, and twiddle factor addressing logic to, for the twiddle factor tables of the initial group of stages, apply an indexed entry of the twiddle factor table to the associated multiplier. The indexed entry begins as a first entry and advances by N entries after every N cycles.

Abstract: The disclosure provides a radar apparatus. The radar apparatus includes a transmitter that transmits a first chirp. The first chirp is scattered by one or more obstacles to generate a first plurality of scattered signals. A plurality of receivers receives the first plurality of scattered signals. Each receiver of the plurality of receivers generates a digital signal in response to a scattered signal of the first plurality of scattered signals. A processor is coupled to the plurality of receivers and receives the digital signals from the plurality of receivers. The processor performs range FFT (fast fourier transform) and angle FFT on the digital signals received from the plurality of receivers to generate a first matrix of complex samples.

Abstract: A frequency modulated continuous wave (FMCW) radar system is provided that includes a receiver configured to generate a digital intermediate frequency (IF) signal, and an interference monitoring component coupled to the receiver to receive the digital IF signal, in which the interference monitoring component is configured to monitor at least one sub-band in the digital IF signal for interference, in which the at least one sub-band does not include a radar signal.

Abstract: A FMCW radar system with a built-in self-test (BIST) system for monitoring includes a receiver, a transmitter, and a frequency synthesizer. A FMCW chirp timing engine controls timing of operations at least one radar component. The BIST system includes at least one switchable coupling for coupling a first plurality of different analog signals including from a first plurality of selected nodes in the receiver or transmitter that are all coupled to a second number of monitor analog-to-digital converters (ADCs). The second number is less than (<) the first plurality of different analog signals. The BIST system includes a monitor timing engine and controller operating synchronously with the chirp timing engine, that includes a software configurable monitoring architecture for generating control signals including for selecting using the switchable coupling which analog signal to forward to the monitor ADC and when the monitor ADC samples the analog signals.

Abstract: A radar system is provided that includes a receive channel configured to receive a reflected signal and to generate a first digital intermediate frequency (IF) signal based on the reflected signal, a reference receive channel configured to receive a reflected signal and to generate a second digital IF signal based on the reflected signal, and digital mismatch compensation circuitry coupled to receive the first digital IF signal and the second digital IF signal, the digital mismatch compensation circuitry configured to process the first digital IF signal and the second digital IF signal to compensate for mismatches between the receive channel and the reference receive channel.

Abstract: A frequency modulated continuous wave (FMCW) radar system is provided that includes a receiver configured to generate a digital intermediate frequency (IF) signal, and an interference monitoring component coupled to the receiver to receive the digital IF signal, in which the interference monitoring component is configured to monitor at least one sub-band in the digital IF signal for interference, in which the at least one sub-band does not include a radar signal.

Abstract: An example method may include receiving, at a device, a first frame over a wireless network and constructing a preliminary data portion of a second frame. The second frame may be configured for transmission over the wireless network. The method may also include in response to the receiving of the first frame at the device, beginning transmission of a header portion of the second frame over the wireless network and after the beginning transmission of the header portion of the second frame, constructing, based on the preliminary data portion, a finalized data portion of the second frame for transmission over the wireless network.

Abstract: Data memory protection is provided for a signal processing system such as a radar system in which the data memory is protected with a common set of parity bits rather than requiring a set of parity bits for each memory word as in Error Correction Coded (ECC) memories. The common set of parity bits may be updated as memory words in the data memory are accessed as part of signal processing of one or more digital signals. The memory protection ensures that in the absence of memory errors the common parity bits are zero at the end of processing the digital signals as long as each word in the data memory that is used for storing the signal processing data is written and read an equal number of times.

Abstract: A radar system is provided that includes a receive channel configured to receive a reflected signal and to generate a first digital intermediate frequency (IF) signal based on the reflected signal, a reference receive channel configured to receive a reflected signal and to generate a second digital IF signal based on the reflected signal, and digital mismatch compensation circuitry coupled to receive the first digital IF signal and the second digital IF signal, the digital mismatch compensation circuitry configured to process the first digital IF signal and the second digital IF signal to compensate for mismatches between the receive channel and the reference receive channel.

Abstract: The disclosure provides a radar apparatus for estimating a position and a velocity of a plurality of obstacles. The radar apparatus includes a slave radar chip. A master radar chip is coupled to the slave radar chip. The master radar chip includes a local oscillator that generates a transmit signal. The slave radar chip receives the transmit signal on a first path and sends the transmit signal back to the master radar chip on a second path. A delay detect circuit is coupled to the local oscillator and receives the transmit signal from the slave radar chip on the second path and the transmit signal from the local oscillator. The delay detect circuit estimates a routing delay from the transmit signal received from the slave radar chip on the second path and from the transmit signal received from the local oscillator.

Abstract: Data memory protection is provided for a signal processing system such as a radar system in which the data memory is protected with a common set of parity bits rather than requiring a set of parity bits for each memory word as in Error Correction Coded (ECC) memories. The common set of parity bits may be updated as memory words in the data memory are accessed as part of signal processing of one or more digital signals. The memory protection ensures that in the absence of memory errors the common parity bits are zero at the end of processing the digital signals as long as each word in the data memory that is used for storing the signal processing data is written and read an equal number of times.

Abstract: A noise-mitigated continuous-wave frequency-modulated radar includes, for example, a transmitter for generating a radar signal, a receiver for receiving a reflected radar signal and comprising a mixer for generating a baseband signal in response to the received radar signal and in response to a local oscillator (LO) signal, and a signal shifter coupled to at least one of the transmitter, LO input of the mixer in the receiver and the baseband signal generated by the mixer. The impact of amplitude noise or phase noise associated with interferers, namely, for example, strong reflections from nearby objects, and electromagnetic coupling from transmit antenna to receive antenna, on the detection of other surrounding objects is reduced by configuring the signal shifter in response to an interferer frequency and phase offset.