Abstract: A switched delay section for an integrated circuit device is disclosed. The switched delay section includes a segmented inductor loop comprising a plurality of segments separated by nodes. A plurality of capacitors are coupled between the segmented inductor loop to provide a plurality of delay sections. An image loop is in electrical communication with the segmented inductor loop. The image loop includes a switch configured to place the plurality of capacitors in one of a high capacitance or a low capacitance state to provide a variable delay value.

Abstract: This frequency tripler system uses a cascade of integrated transistor circuit differential limiting amplifiers and tunable notch filters that can directly serve one or more outputs, such as a direct clock or local oscillator drive. With this topology, filtering is distributed between two or more stages of differential limiting amplifiers and tunable notch filters. This enables suppression of smaller fundamental tone by the differential limiting amplifiers along with the tunable notch filters and yields a strong third harmonic signal to directly drive high performance mixers and digital-to-analog converters.

Abstract: This frequency tripler system uses a cascade of integrated transistor circuit differential limiting amplifiers and tunable notch filters that can directly serve one or more outputs, such as a direct clock or local oscillator drive. With this topology, filtering is distributed between two or more stages of differential limiting amplifiers and tunable notch filters. This enables suppression of smaller fundamental tone by the differential limiting amplifiers along with the tunable notch filters and yields a strong third harmonic signal to directly drive high performance mixers and digital-to-analog converters.

Abstract: A differential tuned inductor and a multilayer tunable transformer for an integrated circuit device for microwave and RF applications are disclosed. The tunable inductor can be used in differential artificial delay lines to achieve delay tuning while preserving impedance matching. The tunable transformer can also be used for mixer drives to achieve wider operational performance.

Abstract: A switched delay section for an integrated circuit device is disclosed. The switched delay section includes a segmented inductor loop comprising a plurality of segments separated by nodes. A plurality of capacitors are coupled between the segmented inductor loop to provide a plurality of delay sections. An image loop is in electrical communication with the segmented inductor loop. The image loop includes a switch configured to place the plurality of capacitors in one of a high capacitance or a low capacitance state to provide a variable delay value.

Abstract: Embodiments of power efficient radio mixers are provided. A generalized impedance matched low-voltage active mixer circuit technique, which utilizes a plurality of commutator cells and transformers, is disclosed. The low voltage active mixer function is coupled to an impedance matched amplifier allowing for insertion of image rejection filtering between the amplifier and the mixing function. The commutator cells can be driven in parallel by common local oscillator (LO) and intermediate frequency (IF) ports combined in parallel to yield highly linear mixers. A multi-channel receiver with a common impedance matched radio frequency (RF) amplifier driving a plurality of commutator cells with multiple LOs and IFs is also disclosed.

Abstract: A power efficient (PE) amplifier includes a cascode amplifier, a transistor amplifier, and a voltage supply. The transistor amplifier includes at least one differential pair of transistors and a plurality of transformers having a primary winding and a tapped secondary winding. The secondary winding is connected across emitters or sources of each transistor pair. The tap of each secondary has a current source. The primary windings of the plurality of transformers are connected in series. The transistor bases or gates are alternating current (AC) grounded. The collector or drain terminal pairs are connected in parallel. The voltage supply is low voltage and supplies a current to the cascode amplifier. The PE amplifier further includes a plurality of current sources which provide a total current to the transistor amplifier. The PE amplifier has, among other things, improved power gain, improved reverse isolation, improved power dissipation, and improved peak differential swing.

Abstract: A transistor amplifier includes at least one differential pair of transistors and a plurality of transformers having a primary winding and a tapped secondary winding. The secondary winding is connected across emitters or sources of each transistor pair. The tap of each secondary has a current source. The primary windings of the plurality of transformers are connected in series. The transistor bases or gates are alternating current (AC) grounded. The collector or drain terminal pairs are connected in parallel. The transistor amplifier exhibits improved input impedance and improved linearity.

Abstract: A power efficient (PE) amplifier includes a cascode amplifier, a transistor amplifier, and a voltage supply. The transistor amplifier includes at least one differential pair of transistors and a plurality of transformers having a primary winding and a tapped secondary winding. The secondary winding is connected across emitters or sources of each transistor pair. The tap of each secondary has a current source. The primary windings of the plurality of transformers are connected in series. The transistor bases or gates are alternating current (AC) grounded. The collector or drain terminal pairs are connected in parallel. The voltage supply is low voltage and supplies a current to the cascode amplifier. The PE amplifier further includes a plurality of current sources which provide a total current to the transistor amplifier. The PE amplifier has, among other things, improved power gain, improved reverse isolation, improved power dissipation, and improved peak differential swing.

Abstract: Embodiments of power efficient radio mixers are provided. A generalized impedance matched low-voltage active mixer circuit technique, which utilizes a plurality of commutator cells and transformers, is disclosed. The low voltage active mixer function is coupled to an impedance matched amplifier allowing for insertion of image rejection filtering between the amplifier and the mixing function. The commutator cells can be driven in parallel by common local oscillator (LO) and intermediate frequency (IF) ports combined in parallel to yield highly linear mixers. A multi-channel receiver with a common impedance matched radio frequency (RF) amplifier driving a plurality of commutator cells with multiple LOs and IFs is also disclosed.

Abstract: A transistor amplifier includes at least one differential pair of transistors and a plurality of transformers having a primary winding and a tapped secondary winding. The secondary winding is connected across emitters or sources of each transistor pair. The tap of each secondary has a current source. The primary windings of the plurality of transformers are connected in series. The transistor bases or gates are alternating current (AC) grounded. The collector or drain terminal pairs are connected in parallel. The transistor amplifier exhibits improved input impedance and improved linearity.

Abstract: A triple-balanced radio frequency (RF) mixer including a plurality of double-balanced mixer cells and a plurality of transformers is disclosed. Each of the plurality of transformers includes a primary and a secondary. Each primary is connected in series. Each secondary is connected across one double-balanced mixer cell of said plurality of double-balanced mixer cells. The triple-balanced RF mixer further includes a local oscillator (LO) port coupled to each of the plurality of double-balanced mixer cells in parallel, an output port coupled to each of the plurality of double-balanced mixer cells in parallel, and at least one non-ideality source providing at least one-non-ideality. The at least one non-ideality is cancelled at the output port.

Abstract: A frequency multiplier, which may include multiple commutator cells, for multiplying an input signal is provided. A frequency doubler is provided that includes at least one transformer. Each of the at least one transformer includes a primary and a secondary. Each secondary includes a center tap. The frequency doubler further includes at least one commutator cell. Each of the at least one commutator cell includes a first differential pair of input terminals and a second differential pair of input terminals. Each primary is connected to the first pair of differential input terminals and each secondary is connected to the second differential pair of input terminals. The frequency doubler further includes at least one current source and at least one ground. The center tap is connected to the at least one ground via the at least one current source.

Abstract: Embodiments of power efficient radio frequency mixers are provided. A generalized impedance matched low-voltage active mixer circuit technique, which utilizes a plurality of commutator cells and transformers, is disclosed. The active mixer techniques are reconfigurable between various operation configurations based, at least in part, on selectively activating at least one of a plurality of commutator cells. The low voltage active mixer function is coupled to an impedance matched amplifier which can be bypassed allowing changes in the gain of the mixer circuit suites while preserving impedance matching.

Abstract: A variable gain amplifier circuit including a first amplifier, a second amplifier, and a variable capacitor connected in series between the first amplifier and the second amplifier is disclosed. As a gain of the variable gain amplifier circuit varies, the input impedance, output impedance, noise figure and third-order output intercept point (OIP3) of the variable gain amplifier circuit remain unchanged.

Abstract: A variable gain amplifier circuit including a first amplifier, a second amplifier, and a variable capacitor connected in series between the first amplifier and the second amplifier is disclosed. As a gain of the variable gain amplifier circuit varies, the input impedance, output impedance, noise figure and third-order output intercept point (OIP3) of the variable gain amplifier circuit remain unchanged.

Abstract: Embodiments of power efficient radio frequency mixers are provided. A generalized impedance matched low-voltage active mixer circuit technique, which utilizes a plurality of commutator cells and transformers, is disclosed. The active mixer techniques are reconfigurable between various operation configurations based, at least in part, on selectively activating at least one of a plurality of commutator cells. The low voltage active mixer function is coupled to an impedance matched amplifier which can be bypassed allowing changes in the gain of the mixer circuit suites while preserving impedance matching.

Abstract: Sequenced switching mitigates impedance variations and signal reflections during switching events by stepping a switch incrementally through a sequence of different states from a start state to at least one intermediate state to an end state. Various architectures, sequencing and step control techniques may permit any degree of mitigation, including to the point of essentially eliminating impedance glitches. Sequential reconfiguration of the structure and/or parameters of one or more switch branches may permit simplification of related programming and circuitry while increasing the lifespan of components spared from unmitigated current and voltage spikes. Each switch branch being transitioned during a switch event may sequence differently than other branches based on the start state, end state and configuration of each branch.

Abstract: An amplifier circuit is disclosed comprising: an input terminal configured to receive a radio frequency input signal; an output terminal configured to provide a radio frequency output signal; a first transistor having a first collector, a first emitter, and a first base; a second transistor having a second collector, a second emitter, and a second base; a bypass switch; and a controller. The first base is connected to the input terminal and the second emitter. The first collector is connected to a circuit voltage supply and the output terminal. The first emitter is connected to ground and to the second base. The second collector is connected to a collector voltage supply. The bypass switch is connected between the first base and the output terminal.

Abstract: Sequenced switching mitigates impedance variations and signal reflections during switching events by stepping a switch incrementally through a sequence of different states from a start state to at least one intermediate state to an end state. Various architectures, sequencing and step control techniques may permit any degree of mitigation, including to the point of essentially eliminating impedance glitches. Sequential reconfiguration of the structure and/or parameters of one or more switch branches may permit simplification of related programming and circuitry while increasing the lifespan of components spared from unmitigated current and voltage spikes. Each switch branch being transitioned during a switch event may sequence differently than other branches based on the start state, end state and configuration of each branch.