Patents by Inventor Kathryn W. Guarini

Kathryn W. Guarini has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040241958
    Abstract: Described is a method for making silicon on sapphire structures, and devices therefrom. The inventive method of forming integrated circuits on a sapphire substrate comprises the steps of providing a device layer on an oxide layer of a temporary substrate; bonding the device layer to a handling substrate; removing the temporary substrate to provide a structure containing the device layer between the oxide layer and the handling substrate; bonding a sapphire substrate to the oxide layer; removing the handling substrate from the structure; and annealing the final structure to provide a substrate comprising the oxide layer between the device layer and the sapphire substrate. The sapphire substrate may comprise bulk sapphire or may be a conventional substrate material with an uppermost sapphire layer.
    Type: Application
    Filed: June 2, 2003
    Publication date: December 2, 2004
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kathryn W. Guarini, Louis L. Hsu, Leathen Shi, Dinkar V. Singh
  • Patent number: 6821826
    Abstract: Three-dimensional (3D) integration schemes of fabricating a 3D integrated circuit in which the pFETs are located on an optimal crystallographic surface for that device and the nFETs are located on a optimal crystallographic surface for that type of device are provided. In accordance with a first 3D integration scheme of the present invention, first semiconductor devices are pre-built on a semiconductor surface of a first silicon-on-insulator (SOI) substrate and second semiconductor devices are pre-built on a semiconductor surface of a second SOI substrate. After pre-building those two structures, the structure are bonded together and interconnect through wafer-via through vias.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: November 23, 2004
    Assignee: International Business Machines Corporation
    Inventors: Victor Chan, Kathryn W. Guarini, Meikei Ieong
  • Patent number: 6803266
    Abstract: A process for passivating the semiconductor-dielectric interface of a MOS structure to reduce the interface state density to a very low level. A particular example is a MOSFET having a tungsten electrode that in the past has prevented passivation of the underlying semiconductor-dielectric interface to an extent sufficient to reduce the interface state density to less than 5×1010/cm2−eV. Though substantially impervious to molecular hydrogen, thin tungsten layers are shown to be pervious to atomic hydrogen, enabling atomic hydrogen to be diffused through a tungsten electrode into an underlying semiconductor-dielectric interface.
    Type: Grant
    Filed: March 20, 2003
    Date of Patent: October 12, 2004
    Assignee: International Business Machines Corporation
    Inventors: Paul M. Solomon, Douglas A. Buchanan, Eduard A. Cartier, Kathryn W. Guarini, Fenton R. McFeely, Huiling Shang, John J. Yourkas
  • Publication number: 20040142578
    Abstract: The co-self-assembly of organic, e.g., block copolymer, and inorganic, e.g., sol-gel, components is employed to create nanometer features of silicon dioxide type materials in thin films on silicon surfaces. In the preferred embodiment, sol-gel chemistry is used to introduce inorganic components (preferably 3-glycidoxy-propyltrimethoxysilane and aluminum-tri-sec-butoxide) into a block copolymer (preferably poly (isoprene-block-ethylene oxide) (PI-b-PEO)), as a structure-directing agent. The inorganic components preferentially migrate to the PEO block and swell the copolymer into different morphologies depending on the amount of sol-gel precursors added. Thin films (e.g., below 100 nm) are created by spin coating the hybrid solution onto a silicon wafer. An inverse hexagonal morphology, for example, is produced in which the polymer forms nanopores within an inorganic matrix. Through heat treatment the organic phase can subsequently be removed leaving an all-inorganic porous nanostructure on the wafer.
    Type: Application
    Filed: March 27, 2003
    Publication date: July 22, 2004
    Inventors: Ulrich Wiesner, Phong Du, Charles T. Black, Kathryn W. Guarini
  • Publication number: 20040124092
    Abstract: The invention provides a method of forming an inorganic porous membrane that includes forming an inorganic membrane material on a substrate, forming a porous self-assembled material on the inorganic membrane material, and patterning the membrane material using the porous self-assembled material as a mask.
    Type: Application
    Filed: December 30, 2002
    Publication date: July 1, 2004
    Inventors: Charles T. Black, Kathryn W. Guarini
  • Patent number: 6603181
    Abstract: A MOS structure processed to have a semiconductor-dielectric interface that is passivated to reduce the interface state density. An example is a MOSFET having a gate dielectric on which an electrode is present that is substantially impervious to molecular hydrogen, but sufficiently thin to be pervious to atomic hydrogen, enabling atomic hydrogen to be diffused therethrough into an underlying semiconductor-dielectric interface. Atomic hydrogen diffusion can be achieved by subjecting such an electrode to hydrogen plasma, forming the electrode of an aluminum-tungsten alloy in the presence of hydrogen, and implanting atomic hydrogen into the electrode. The latter two techniques are each followed by an anneal to cause the atomic hydrogen to diffuse through the electrode and into the semiconductor-dielectric interface.
    Type: Grant
    Filed: January 16, 2001
    Date of Patent: August 5, 2003
    Assignee: International Business Machines Corporation
    Inventors: Paul M. Solomon, Douglas A. Buchanan, Eduard A. Cartier, Kathryn W. Guarini, Fenton R. McFeely, Huiling Shang, John J. Yourkas
  • Publication number: 20030132492
    Abstract: A process for passivating the semiconductor-dielectric interface of a MOS structure to reduce the interface state density to a very low level. A particular example is a MOSFET having a tungsten electrode that in the past has prevented passivation of the underlying semiconductor-dielectric interface to an extent sufficient to reduce the interface state density to less than 5x1010/cm2-eV. Though substantially impervious to molecular hydrogen, thin tungsten layers are shown to be pervious to atomic hydrogen, enabling atomic hydrogen to be diffused through a tungsten electrode into an underlying semiconductor-dielectric interface.
    Type: Application
    Filed: March 20, 2003
    Publication date: July 17, 2003
    Applicant: International Business Machines Corporation
    Inventors: Paul M. Solomon , Douglas A. Buchanan , Eduard A. Cartier , Kathryn W. Guarini , Fenton R. McFeely , Huiling Shang , John J. Yourkas
  • Patent number: 6506660
    Abstract: Described is a method of increasing the capacitance of semiconductor capacitors by providing a first solid-state electrode pattern on a semiconductor medium, etching topographic features on said first electrode pattern in a manner effective in increasing the surface area of said first electrode pattern, depositing a dielectric layer upon said electrode pattern that substantially conforms to said topographic features, and depositing a second solid-state electrode pattern upon said dielectric layer and sufficiently insulated from said first solid-state electrode pattern so as to create a capacitance with said first solid-state electrode pattern.
    Type: Grant
    Filed: November 13, 2001
    Date of Patent: January 14, 2003
    Assignee: International Business Machines Corporation
    Inventors: Steven J. Holmes, Charles Black, David J. Frank, Toshiharu Furukawa, Mark C. Hakey, David V. Horak, William Hsioh-Lien Ma, Keith R. Milkove, Kathryn W. Guarini
  • Publication number: 20020094643
    Abstract: A process for passivating the semiconductor-dielectric interface of a MOS structure to reduce the interface state density to a very low level. A particular example is a MOSFET having a tungsten electrode that in the past has prevented passivation of the underlying semiconductor-dielectric interface to an extent sufficient to reduce the interface state density to less than 5×1010/cm2-eV. Though substantially impervious to molecular hydrogen, thin tungsten layers are shown to be pervious to atomic hydrogen, enabling atomic hydrogen to be diffused through a tungsten electrode into an underlying semiconductor-dielectric interface.
    Type: Application
    Filed: January 16, 2001
    Publication date: July 18, 2002
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Paul M. Solomon, Douglas A. Buchanan, Eduard A. Cartier, Kathryn W. Guarini, Fenton R. McFeely, Huiling Shang, John J. Yourkas
  • Publication number: 20020058394
    Abstract: Described is a method of increasing the capacitance of semiconductor capacitors by providing a first solid-state electrode pattern on a semiconductor medium, etching topographic features on said first electrode pattern in a manner effective in increasing the surface area of said first electrode pattern, depositing a dielectric layer upon said electrode pattern that substantially conforms to said topographic features, and depositing a second solid-state electrode pattern upon said dielectric layer and sufficiently insulated from said first solid-state electrode pattern so as to create a capacitance with said first solid-state electrode pattern.
    Type: Application
    Filed: November 13, 2001
    Publication date: May 16, 2002
    Applicant: International Business Machines Corporation
    Inventors: Steven J. Holmes, Charles Black, David J. Frank, Toshiharu Furukawa, Mark C. Hakey, David V. Horak, William Hsioh-Lien Ma, Keith R. Milkove, Kathryn W. Guarini
  • Patent number: 6358813
    Abstract: Described is a method of increasing the capacitance of semiconductor capacitors by providing a first solid-state electrode pattern on a semiconductor medium, etching topographic features on said first electrode pattern in a manner effective in increasing the surface area of said first electrode pattern, depositing a dielectric layer upon said electrode pattern that substantially conforms to said topographic features, and depositing a second solid-state electrode pattern upon said dielectric layer and sufficiently insulated from said first solid-state electrode pattern so as to create a capacitance with said first solid-state electrode pattern.
    Type: Grant
    Filed: November 15, 2000
    Date of Patent: March 19, 2002
    Assignee: International Business Machines Corporation
    Inventors: Steven J. Holmes, Charles Black, David J. Frank, Toshiharu Furukawa, Mark C. Hakey, David V. Horak, William Hsioh-Lien Ma, Keith R. Milkove, Kathryn W. Guarini