Abstract: A method for forming a device includes forming a hole pattern in a resist layer disposed over a substrate. The substrate includes contact regions disposed over a major surface of the substrate and a dielectric layer disposed over the contact regions. The resist layer is disposed over the dielectric layer and the hole pattern includes through openings in the resist layer that are aligned with the contact regions. The through openings include a first through opening having a first critical dimension and a second through opening having a second critical dimension greater than the first critical dimension. The method includes modifying the hole pattern by depositing a material including silicon within the through openings by exposing the hole pattern to a first plasma generated from a gas mixture including SiCl4 and hydrogen, and then etching holes in the dielectric layer through the modified hole pattern, exposing the contact regions.

Abstract: A method of forming a semiconductor device includes forming, over a hardmask layer and an underlying layer of a substrate, a pattern of first trenches between adjacent template lines, each of the first trenches exposing a portion of the hardmask layer, and each of the template lines including a mandrel and spacers on sidewalls of the mandrel; forming a pattern of first blocks over the pattern of the first trenches and the template lines, the first blocks dividing the first trenches to form a pattern of first stencil trenches; transferring the pattern of first stencil trenches to the hardmask layer to form a pattern of first hardmask trenches, each of the first hardmask trenches exposing a portion of the underlying layer; forming a first fill layer filling the first hardmask trenches and exposing the mandrels; selectively removing the mandrels to form second trenches, each of the second trenches exposing a portion of the hardmask layer; and forming a conformal liner in the second trenches and over a surface of

Abstract: A method of processing a substrate that includes: forming recesses in a first mask layer over a mask stack including a lower hardmask, a middle mask, and an upper hardmask, the recesses defining an initial pattern including a plurality of spacer structures, each of the spacer structures having a first sidewall and an opposite second sidewall, the first sidewall having a different height from the second sidewall; etching the upper hardmask, selectively to the middle mask, to transfer the initial pattern to the upper hardmask; etching the middle mask, selectively to the lower hardmask and the patterned upper hardmask, to transfer a pattern of the patterned upper hardmask to the middle mask; and etching the lower hardmask, selectively to the patterned middle mask, to transfer a pattern of the patterned middle mask to the lower hardmask.

Abstract: Methods are provided herein for improving oxygen content control in a Metal-Insulator-Metal (MIM) stack of an RERAM cell, while also maintaining throughput. More specifically, a single chamber solution is provided herein for etching and encapsulating the MIM stack of an RERAM cell to control the oxygen content in the memory cell dielectric of the RERAM cell. According to one embodiment, a non-oxygen-containing dielectric encapsulation layer is deposited onto the MIM stack in-situ while the substrate remains within the processing chamber used to etch the MIM stack. By etching the MIM stack and depositing the encapsulation layer within the same processing chamber, the techniques described herein minimize the exposure of the memory cell dielectric to oxygen, while maintaining throughput.

Abstract: A method of forming a semiconductor device includes depositing a first layer over a substrate and patterning the first layer using an extreme ultraviolet (EUV) lithography process to form a patterned layer and expose portions of the substrate. The method includes, in a plasma processing chamber, generating a first plasma from a gas mixture including SiCl4 and one or more of argon, helium, nitrogen, and hydrogen. The method includes exposing the substrate to the first plasma to deposit a second layer including silicon over the patterned layer.

Abstract: A method of forming a semiconductor device includes receiving a substrate in a plasma chamber, the substrate comprising an EUV patterned first mask material comprising a metal-based resist (MBR) and an underlying layer disposed between the substrate and the first mask material; depositing, selectively, a second mask material on the first masking layer using a first plasma comprising a source gas that reacts selectively with the first masking layer relative to the underlying layer; and etching the portion of the underlying layer to form a patterned underlying layer using the second masking layer and the first masking layer as an etch mask.

Abstract: A method is described for patterning a dielectric layer disposed over a semiconductor substrate layer. The patterning process includes forming a patterned hard mask layer over the dielectric layer, the patterned hard mask layer exposing a portion of a major surface of the dielectric layer. A portion of the dielectric layer is removed by a cyclic etch process, where performing one cycle of the cyclic etch process comprises forming a capping layer selectively over the patterned hard mask layer and performing a timed etch process that removes material from the dielectric layer. In another method, the deposition over the hard mask and the removal of the portion of the dielectric layer are performed concurrently.

Abstract: A method of processing a substrate that includes: etching a recess in the substrate using a metal hard mask (MHM) layer as an etch mask, the substrate including a dielectric layer over a conductive layer the includes a first conductive material, a portion of the MHM layer remaining over top surfaces of the dielectric layer after the etching; depositing a sacrificial fill over the substrate to at least partially fill the recess; removing the remaining portion of the MHM layer to expose the top surfaces while protecting the recess with the sacrificial fill; removing the sacrificial fill from the recess after removing the MHM layer, the removing of the sacrificial fill including exposing a portion of the conductive layer; and depositing a second conductive material to fill the recess, the depositing of the second conductive material providing an electrical connection between the conductive layer and the second conductive material.

Abstract: A method of processing a substrate that includes: depositing a photoactive metal-based hard mask (photo-MHM) over an underlying layer, the underlying layer formed over a substrate, the photo-MHM including a metal; depositing a dielectric over the photo-MHM; etching a portion of the dielectric to form a first feature; depositing a spacer material over the first feature; etching the spacer material to expose top surfaces of the dielectric and a first portion of the photo-MHM; exposing the photo-MHM to a first ultraviolet light (UV) radiation through a first photomask, a first unmasked region of the photo-MHM being photoreacted due to the exposure to the first UV radiation; after the exposure, developing the photo-MHM to form a second feature in the photo-MHM; and etching the underlying layer using the photo-MHM as an etch mask.

Abstract: A method of processing a substrate that includes: forming a first plurality of lines and a first plurality of recesses, each of the plurality of lines being separated from an adjacent one of the plurality of lines by one of the plurality of recesses, the first plurality of lines including a first material and formed over a to-be-patterned layer; performing a cyclic process including: depositing a mask material over the first plurality of lines and within the first plurality of recesses, the mask material deposited defining a second plurality of lines, each of the second plurality of lines dividing one of the first plurality of recesses to form a second plurality of recesses; and performing a trimming process to increase critical dimensions of the second plurality of recesses; and patterning the to-be-patterned layer using the first plurality of lines and the second plurality of lines as an etch mask.

Abstract: A method for patterning a substrate includes: forming a first photoresist etch mask with an extreme ultraviolet (EUV) lithography process, the first photoresist etch mask including first through openings, the first photoresist etch mask including a metal-based photoresist material; forming a second photoresist etch mask over the first photoresist etch mask, the second photoresist etch mask including second through openings; and forming first openings, through the first and the second photoresist etch masks, in a region of the substrate that vertically overlaps both the first through openings and the second through openings.

Abstract: Methods are provided herein for forming spacers on a patterned substrate. A self-aligned multiple patterning (SAMP) process is utilized for patterning structures, spacers formed adjacent mandrels, on a substrate. In one embodiment, a novel approach of etching titanium oxide (TiO2) spacers is provided. Highly anisotropic etching of the spacer along with a selective top deposition is provided. In one embodiment, an inductively coupled plasma (ICP) etch tool is utilized. The etching process may be achieved as a one-step etching process. More particularly, a protective layer may be selectively formed on the top of the spacer to protect the mandrel as well as minimize the difference of the etching rates of the spacer top and the spacer bottom. In one embodiment, the techniques may be utilized to etch TiO2 spacers formed along amorphous silicon mandrels using an ICP etch tool utilizing a one-step etch process.

Abstract: Improved process flows and methods are provided herein for trimming structures formed on a patterned substrate. In the disclosed process flows and methods, a self-aligned multiple patterning (SAMP) process is utilized for patterning structures, such as mandrels, on a substrate. After the structures are patterned, an atomic layer deposition (ALD) process is used to form a spacer layer on the patterned structures. In the SAMP process disclosed herein, a critical dimension (CD) of the patterned structures is trimmed concurrently with, and as a result of, the formation of the spacer layer by controlling various ALD process parameters and conditions. By trimming the patterned structures in situ of the ALD chamber used to form the spacer layer on the patterned structures, the improved process flows and methods described herein provide a CD trim method that does not adversely affect the pattern profile or process throughput.

Abstract: A method for plasma processing that includes: loading a dummy wafer between a focus ring positioned within a plasma process chamber; depositing a material layer over the focus ring by a plasma deposition process within the plasma process chamber; removing the dummy wafer from the plasma process chamber, and loading a substrate to be processed between the focus ring with the material layer within the plasma process chamber and performing a plasma process on the substrate.

Abstract: A method is described for patterning a dielectric layer disposed over a semiconductor substrate layer. The patterning process includes forming a patterned hard mask layer over the dielectric layer, the patterned hard mask layer exposing a portion of a major surface of the dielectric layer. A portion of the dielectric layer is removed by a cyclic etch process, where performing one cycle of the cyclic etch process comprises forming a capping layer selectively over the patterned hard mask layer and performing a timed etch process that removes material from the dielectric layer. In another method, the deposition over the hard mask and the removal of the portion of the dielectric layer are performed concurrently.

Abstract: A method of plasma etching includes receiving, by a plasma processing apparatus, a substrate into a processing chamber of the plasma processing apparatus. The substrate includes an etchable layer and a first mask layer overlying the etchable layer. The first mask layer includes a plurality of openings vertically aligned with exposed regions of the etchable layer. The method further includes forming, in the processing chamber, a protective layer over the first mask layer and the exposed regions and etching, in the processing chamber, the protective layer and the exposed regions to remove the protective layer and form recesses in the etchable layer.

Abstract: A process flow is utilized for patterning of dual damascene structures in BEOL process steps. Conductor vias are inversely patterned in the form of pillars that are formed before the final dielectric stack is deposited. The final dielectric stack may include a low-k dielectric and the conductor may be ruthenium. The vias may be formed by forming conductor pillars in patterned voids of a sacrificial layer. After the pillars are formed, certain areas between the pillars can then be backfilled with a dielectric, such as for example, a low-k dielectric material. The trench conductor of the dual damascene structure may then be formed. The sacrificial dielectric may then be removed and an additional layer of low-k dielectric material can then be deposited or coated on the structure to provide the final structure having the dual damascene vias and trenches filled with the conductor surrounded by low-k material.

Abstract: A method for forming a device includes forming a hole pattern in a resist layer disposed over a substrate. The substrate includes contact regions disposed over a major surface of the substrate and a dielectric layer disposed over the contact regions. The resist layer is disposed over the dielectric layer and the hole pattern includes through openings in the resist layer that are aligned with the contact regions. The through openings include a first through opening having a first critical dimension and a second through opening having a second critical dimension greater than the first critical dimension. The method includes modifying the hole pattern by depositing a material including silicon within the through openings by exposing the hole pattern to a first plasma generated from a gas mixture including SiCl4 and hydrogen, and then etching holes in the dielectric layer through the modified hole pattern, exposing the contact regions.

Abstract: Improved process flows and methods are provided herein for trimming structures formed on a patterned substrate. In the disclosed process flows and methods, a self-aligned multiple patterning (SAMP) process is utilized for patterning structures, such as mandrels, on a substrate. After the structures are patterned, an atomic layer deposition (ALD) process is used to form a spacer layer on the patterned structures. In the SAMP process disclosed herein, a critical dimension (CD) of the patterned structures is trimmed concurrently with, and as a result of, the formation of the spacer layer by controlling various ALD process parameters and conditions. By trimming the patterned structures in situ of the ALD chamber used to form the spacer layer on the patterned structures, the improved process flows and methods described herein provide a CD trim method that does not adversely affect the pattern profile or process throughput.

Abstract: Improved methods are provided for transferring a photoresist pattern onto one or more underlying layers. In the disclosed embodiments, etch selectivity between a photoresist layer and one or more underlying layers is improved by pre-treating the underlying layer(s) with a plasma before the photoresist layer is deposited and patterned to form a photoresist pattern. The plasma modifies the underlying layer(s) by implanting ions into the underlying layer(s) to form a modified layer. When the modified layer is subsequently etched to transfer the photoresist pattern onto the modified layer, the presence of ions within the modified layer increases the etch rate of the modified layer, compared to the etch rate that the underlying layer(s) would have exhibited without plasma pre-treatment. The increased etch rate of the modified layer improves etch selectivity between the photoresist layer and the modified layer and mitigates defects during the photoresist pattern transfer process.