Patents by Inventor Katsuaki Ookoshi

Katsuaki Ookoshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160240543
    Abstract: A semiconductor device manufacturing method includes: forming an element isolation insulating film in a semiconductor substrate; forming a first film on a surface of the semiconductor substrate; forming a second film on the element isolation insulating film and on the first film; forming a first resist pattern that includes a first open above the element isolation insulating film in a first region; removing the second film on the element isolation insulating film in the first region to separate the second film in the first region into a plurality of parts by performing first etching; forming a third film on the second film in the first region; forming a first gate electrode on the third film in the first region; and forming a first insulating film that includes the first to third films under the first gate electrode by patterning the first to third films.
    Type: Application
    Filed: April 21, 2016
    Publication date: August 18, 2016
    Inventors: Satoshi Torii, Hideaki Matsumura, Hikaru Kokura, Etsuro Kawaguchi, Katsuaki Ookoshi, Yuka Kase, Kengo Inoue
  • Patent number: 9349600
    Abstract: A semiconductor device manufacturing method includes: forming an element isolation insulating film in a semiconductor substrate; forming a first film on a surface of the semiconductor substrate; forming a second film on the element isolation insulating film and on the first film; forming a first resist pattern that includes a first open above the element isolation insulating film in a first region; removing the second film on the element isolation insulating film in the first region to separate the second film in the first region into a plurality of parts by performing first etching; forming a third film on the second film in the first region; forming a first gate electrode on the third film in the first region; and forming a first insulating film that includes the first to third films under the first gate electrode by patterning the first to third films.
    Type: Grant
    Filed: November 19, 2014
    Date of Patent: May 24, 2016
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Satoshi Torii, Hideaki Matsumura, Hikaru Kokura, Etsuro Kawaguchi, Katsuaki Ookoshi, Yuka Kase, Kengo Inoue
  • Publication number: 20150137211
    Abstract: A semiconductor device manufacturing method includes: forming an element isolation insulating film in a semiconductor substrate; forming a first film on a surface of the semiconductor substrate; forming a second film on the element isolation insulating film and on the first film; forming a first resist pattern that includes a first open above the element isolation insulating film in a first region; removing the second film on the element isolation insulating film in the first region to separate the second film in the first region into a plurality of parts by performing first etching; forming a third film on the second film in the first region; forming a first gate electrode on the third film in the first region; and forming a first insulating film that includes the first to third films under the first gate electrode by patterning the first to third films.
    Type: Application
    Filed: November 19, 2014
    Publication date: May 21, 2015
    Inventors: Satoshi TORII, Hideaki MATSUMURA, Hikaru KOKURA, Etsuro KAWAGUCHI, Katsuaki OOKOSHI, Yuka KASE, Kengo INOUE
  • Patent number: 8980710
    Abstract: An impurity layer is formed in a first region of a semiconductor substrate, a silicon layer is grown on the semiconductor substrate, a tunnel gate insulating film is formed on a first silicon layer of a second region, a first conductor layer is formed on the tunnel gate insulating film, a first silicon oxide film and a silicon nitride film are formed on a second silicon layer, in a reduced pressure state, oxygen and hydrogen are independently introduced into an oxidation furnace to expose the silicon nitride film to active species of the oxygen and active species of the hydrogen to thereby oxidize the silicon nitride film to form a second silicon oxide film, a gate insulating film is formed on the silicon layer of the first region, a second conductor layer is formed on the second silicon oxide film and on the gate insulating film, the second conductor layer and the first conductor layer of the second region are patterned to form a stack gate of a nonvolatile memory transistor, and the second conductor layer a
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: March 17, 2015
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Taiji Ema, Mitsuaki Hori, Kazushi Fujita, Makoto Yasuda, Katsuaki Ookoshi
  • Publication number: 20140377921
    Abstract: An impurity layer is formed in a first region of a semiconductor substrate, a silicon layer is grown on the semiconductor substrate, a tunnel gate insulating film is formed on a first silicon layer of a second region, a first conductor layer is formed on the tunnel gate insulating film, a first silicon oxide film and a silicon nitride film are formed on a second silicon layer, in a reduced pressure state, oxygen and hydrogen are independently introduced into an oxidation furnace to expose the silicon nitride film to active species of the oxygen and active species of the hydrogen to thereby oxidize the silicon nitride film to form a second silicon oxide film, a gate insulating film is formed on the silicon layer of the first region, a second conductor layer is formed on the second silicon oxide film and on the gate insulating film, the second conductor layer and the first conductor layer of the second region are patterned to form a stack gate of a nonvolatile memory transistor, and the second conductor layer a
    Type: Application
    Filed: May 30, 2014
    Publication date: December 25, 2014
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Taiji Ema, Mitsuaki Hori, Kazushi Fujita, Makoto Yasuda, Katsuaki Ookoshi
  • Patent number: 8497191
    Abstract: A semiconductor device in which selectivity in epitaxial growth is improved. There is provided a semiconductor device comprising a gate electrode formed over an Si substrate, which is a semiconductor substrate, with a gate insulating film therebetween and an insulating layer formed over sides of the gate electrode and containing a halogen element. With this semiconductor device, a silicon nitride film which contains the halogen element is formed over the sides of the gate electrode when an SiGe layer is formed over the Si substrate. Therefore, the SiGe layer epitaxial-grows over the Si substrate with high selectivity. As a result, an OFF-state leakage current which flows between, for example, the gate electrode and source/drain regions is suppressed and a manufacturing process suitable for actual mass production is established.
    Type: Grant
    Filed: October 14, 2008
    Date of Patent: July 30, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Masahiro Fukuda, Yosuke Shimamune, Masaaki Koizuka, Katsuaki Ookoshi
  • Patent number: 8481383
    Abstract: A semiconductor device includes an NMOS transistor and a PMOS transistor. The NMOS transistor includes a channel area formed in a silicon substrate, a gate electrode formed on a gate insulating film in correspondence with the channel area, and a source area and a drain area formed in the silicon substrate having the channel area situated therebetween. The PMOS transistor includes another channel area formed in the silicon substrate, another gate electrode formed on another gate insulating film in correspondence with the other channel area, and another source area and another drain area formed in the silicon substrate having the other channel area situated therebetween. The gate electrode has first sidewall insulating films. The other gate electrode has second sidewall insulating films. The distance between the second sidewall insulating films and the silicon substrate is greater than the distance between the first sidewall insulating films and the silicon substrate.
    Type: Grant
    Filed: February 10, 2011
    Date of Patent: July 9, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Hiroyuki Ohta, Katsuaki Ookoshi
  • Patent number: 8409958
    Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a gate electrode on a semiconductor substrate; forming a dopant implantation area in the semiconductor substrate by implanting a dopant in the semiconductor substrate, using the gate electrode as a mask; forming sidewalls on the gate electrode; forming a first recess by etching the semiconductor substrate, using the gate electrode and the sidewalls as a mask; forming a second recess by removing the dopant implantation area positioned below the sidewalls; and forming a source area and a drain area by causing a semiconductor material to grow in the first recess and the second recess.
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: April 2, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Katsuaki Ookoshi, Masatoshi Nishikawa, Yosuke Shimamune
  • Publication number: 20120279451
    Abstract: A method of manufacturing a semiconductor device has supplying a first reactant gas into buffer chamber provided in a reaction chamber of the film deposition apparatus to form a first film over an inner wall surface of the buffer chamber, and supplying a second reactant gas into the reaction chamber to form a second film over a semiconductor substrate.
    Type: Application
    Filed: June 28, 2012
    Publication date: November 8, 2012
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Katsuaki Ookoshi
  • Patent number: 8232217
    Abstract: A method of manufacturing a semiconductor device has supplying a first reactant gas into buffer chamber provided in a reaction chamber of the film deposition apparatus to form a first film over an inner wall surface of the buffer chamber, and supplying a second reactant gas into the reaction chamber to form a second film over a semiconductor substrate.
    Type: Grant
    Filed: July 17, 2008
    Date of Patent: July 31, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Katsuaki Ookoshi
  • Publication number: 20120058610
    Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a gate electrode on a semiconductor substrate; forming a dopant implantation area in the semiconductor substrate by implanting a dopant in the semiconductor substrate, using the gate electrode as a mask; forming sidewalls on the gate electrode; forming a first recess by etching the semiconductor substrate, using the gate electrode and the sidewalls as a mask; forming a second recess by removing the dopant implantation area positioned below the sidewalls; and forming a source area and a drain area by causing a semiconductor material to grow in the first recess and the second recess.
    Type: Application
    Filed: July 26, 2011
    Publication date: March 8, 2012
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Katsuaki Ookoshi, Masatoshi Nishikawa, Yosuke Shimamune
  • Publication number: 20110136307
    Abstract: A semiconductor device includes an NMOS transistor and a PMOS transistor. The NMOS transistor includes a channel area formed in a silicon substrate, a gate electrode formed on a gate insulating film in correspondence with the channel area, and a source area and a drain area formed in the silicon substrate having the channel area situated therebetween. The PMOS transistor includes another channel area formed in the silicon substrate, another gate electrode formed on another gate insulating film in correspondence with the other channel area, and another source area and another drain area formed in the silicon substrate having the other channel area situated therebetween. The gate electrode has first sidewall insulating films. The other gate electrode has second sidewall insulating films. The distance between the second sidewall insulating films and the silicon substrate is greater than the distance between the first sidewall insulating films and the silicon substrate.
    Type: Application
    Filed: February 10, 2011
    Publication date: June 9, 2011
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Hiroyuki OHTA, Katsuaki OOKOSHI
  • Patent number: 7906798
    Abstract: A semiconductor device includes an NMOS transistor and a PMOS transistor. The NMOS transistor includes a channel area formed in a silicon substrate, a gate electrode formed on a gate insulating film in correspondence with the channel area, and a source area and a drain area formed in the silicon substrate having the channel area situated therebetween. The PMOS transistor includes another channel area formed in the silicon substrate, another gate electrode formed on another gate insulating film in correspondence with the other channel area, and another source area and another drain area formed in the silicon substrate having the other channel area situated therebetween. The gate electrode has first sidewall insulating films. The other gate electrode has second sidewall insulating films. The distance between the second sidewall insulating films and the silicon substrate is greater than the distance between the first sidewall insulating films and the silicon substrate.
    Type: Grant
    Filed: December 4, 2007
    Date of Patent: March 15, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Hiroyuki Ohta, Katsuaki Ookoshi
  • Patent number: 7883960
    Abstract: A method of manufacturing a semiconductor device includes forming a conductive layer over a semiconductor substrate, selectively removing the conductive layer for forming a resistance element and a gate electrode, forming sidewall spacers over sidewalls of the remaining conductive layer, forming a first insulating film containing a nitrogen over the semiconductor substrate having the sidewall spacers, implanting ions in the semiconductor substrate through the first insulating film, forming a second insulating film containing a nitrogen over the first insulating film after implanting ions in the semiconductor substrate through the first insulating film, and selectively removing the first and the second insulating film such that at least a part of the first and the second insulating films is remained over the semiconductor substrate and over the conductive layer.
    Type: Grant
    Filed: March 24, 2009
    Date of Patent: February 8, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Masatoshi Fukuda, Akiyoshi Hatada, Katsuaki Ookoshi, Kenichi Okabe, Tomonari Yamamoto
  • Patent number: 7678641
    Abstract: There is provided a semiconductor device having a device isolation region of STI structure formed on a silicon substrate so as to define a device region, wherein the device isolation region comprises a device isolation trench formed in the silicon substrate, and a device isolation insulation film filling the device isolation trench. At least a surface part of the device isolation insulation film is formed of an HF-resistant film.
    Type: Grant
    Filed: August 25, 2005
    Date of Patent: March 16, 2010
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Toshifumi Mori, Katsuaki Ookoshi, Takashi Watanabe, Hiroyuki Ohta
  • Patent number: 7678711
    Abstract: A SiO2 film is formed on a semiconductor substrate. Then, a SiN film is formed on the SiO2 film. In this event bis(tertiary butyl amino) silane and NH3 are used as a material gas, and the film forming temperature is set to 600° C. or lower.
    Type: Grant
    Filed: June 8, 2005
    Date of Patent: March 16, 2010
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Mitsuaki Hori, Hiroyuki Ohta, Katsuaki Ookoshi
  • Patent number: 7679147
    Abstract: A semiconductor device in which selectivity in epitaxial growth is improved. There is provided a semiconductor device comprising a gate electrode formed over an Si substrate, which is a semiconductor substrate, with a gate insulating film therebetween and an insulating layer formed over sides of the gate electrode and containing a halogen element. With this semiconductor device, a silicon nitride film which contains the halogen element is formed over the sides of the gate electrode when an SiGe layer is formed over the Si substrate. Therefore, the SiGe layer epitaxial-grows over the Si substrate with high selectivity. As a result, an OFF-state leakage current which flows between, for example, the gate electrode and source/drain regions is suppressed and a manufacturing process suitable for actual mass production is established.
    Type: Grant
    Filed: August 28, 2008
    Date of Patent: March 16, 2010
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Masahiro Fukuda, Yosuke Shimamune, Masaaki Koizuka, Katsuaki Ookoshi
  • Publication number: 20090311838
    Abstract: A method of manufacturing a semiconductor device includes forming a conductive layer over a semiconductor substrate, selectively removing the conductive layer for forming a resistance element and a gate electrode, forming sidewall spacers over sidewalls of the remaining conductive layer, forming a first insulating film containing a nitrogen over the semiconductor substrate having the sidewall spacers, implanting ions in the semiconductor substrate through the first insulating film, forming a second insulating film containing a nitrogen over the first insulating film after implanting ions in the semiconductor substrate through the first insulating film, and selectively removing the first and the second insulating film such that at least a part of the first and the second insulating films is remained over the semiconductor substrate and over the conductive layer.
    Type: Application
    Filed: March 24, 2009
    Publication date: December 17, 2009
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventors: Masatoshi FUKUDA, Akiyoshi HATADA, Katsuaki OOKOSHI, Kenichi OKABE, Tomonari YAMAMOTO
  • Publication number: 20090117715
    Abstract: A semiconductor device in which selectivity in epitaxial growth is improved. There is provided a semiconductor device comprising a gate electrode formed over an Si substrate, which is a semiconductor substrate, with a gate insulating film therebetween and an insulating layer formed over sides of the gate electrode and containing a halogen element. With this semiconductor device, a silicon nitride film which contains the halogen element is formed over the sides of the gate electrode when an SiGe layer is formed over the Si substrate. Therefore, the SiGe layer epitaxial-grows over the Si substrate with high selectivity. As a result, an OFF-state leakage current which flows between, for example, the gate electrode and source/drain regions is suppressed and a manufacturing process suitable for actual mass production is established.
    Type: Application
    Filed: October 14, 2008
    Publication date: May 7, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Masahiro Fukuda, Yosuke Shimamune, Masaaki Koizuka, Katsuaki Ookoshi
  • Publication number: 20090045471
    Abstract: A semiconductor device in which selectivity in epitaxial growth is improved. There is provided a semiconductor device comprising a gate electrode formed over an Si substrate, which is a semiconductor substrate, with a gate insulating film therebetween and an insulating layer formed over sides of the gate electrode and containing a halogen element. With this semiconductor device, a silicon nitride film which contains the halogen element is formed over the sides of the gate electrode when an SiGe layer is formed over the Si substrate. Therefore, the SiGe layer epitaxial-grows over the Si substrate with high selectivity. As a result, an OFF-state leakage current which flows between, for example, the gate electrode and source/drain regions is suppressed and a manufacturing process suitable for actual mass production is established.
    Type: Application
    Filed: August 28, 2008
    Publication date: February 19, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Masahiro Fukuda, Yosuke Shimamune, Masaaki Koizuka, Katsuaki Ookoshi