Patents by Inventor Katsuaki Saito

Katsuaki Saito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10781902
    Abstract: For a gear train GL including a drive gear 33 and an idler gear 34 engaged with each other and a lock gear 35, provided are a first drive means 3A configured to linearly drive the lock gear 35 in forward and backward directions, a second drive means 3B configured to rotationally drive the drive gear 33 in normal and reverse directions, and a controller C configured to control the both drive means 3A and 3B. The controller C starts driving the lock gear 35 at the time of an unlocking operation, from an engagement position toward the disengagement position through the first drive means 3A, and when the drive is started, the controller C drives the drive gear 33 into one of normal and reverse directions and into the other direction through the second drive means 3B with a polarity reversal in a predetermined cycles T1 and T2.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: September 22, 2020
    Assignee: SINFONIA TECHNOLOGY CO., LTD.
    Inventors: Masaharu Tsujimura, Katsuaki Saito
  • Patent number: 10374414
    Abstract: A semiconductor power module with which it is possible to suppress the influence of noise given from a main terminal to a control terminal is provided. At least any one of main terminals (positive electrode terminal, negative electrode terminal, alternating current terminal) is so configured that the main terminal includes two parts extended in a common direction. The two parts are, for example, formed of a single component having such as a shape that the component is bifurcated from the outside toward the inside of the semiconductor power module or two different components. The two parts are so structured that the parts are extended in a common direction. Control terminals (gate signal terminal and emitter signal terminal) are so arranged that a laminated portion of the control terminals is sandwiched between one and the other of the two parts to configure the semiconductor power module.
    Type: Grant
    Filed: December 23, 2015
    Date of Patent: August 6, 2019
    Assignee: HITACHI POWER SEMICONDUCTOR DEVICE, LTD.
    Inventors: Keisuke Horiuchi, Daisuke Kawase, Masamitsu Inaba, Katsuaki Saito
  • Publication number: 20180283512
    Abstract: For a gear train GL including a drive gear 33 and an idler gear 34 engaged with each other and a lock gear 35, provided are a first drive means 3A configured to linearly drive the lock gear 35 in forward and backward directions, a second drive means 3B configured to rotationally drive the drive gear 33 in normal and reverse directions, and a controller C configured to control the both drive means 3A and 3B. The controller C starts driving the lock gear 35 at the time of an unlocking operation, from an engagement position toward the disengagement position through the first drive means 3A, and when the drive is started, the controller C drives the drive gear 33 into one of normal and reverse directions and into the other direction through the second drive means 3B with a polarity reversal in a predetermined cycles T1 and T2.
    Type: Application
    Filed: March 29, 2018
    Publication date: October 4, 2018
    Applicant: SINFONIA TECHNOLOGY CO., LTD.
    Inventors: Masaharu Tsujimura, Katsuaki Saito
  • Publication number: 20160190915
    Abstract: A semiconductor power module with which it is possible to suppress the influence of noise given from a main terminal to a control terminal is provided. At least any one of main terminals (positive electrode terminal, negative electrode terminal, alternating current terminal) is so configured that the main terminal includes two parts extended in a common direction. The two parts are, for example, formed of a single component having such as a shape that the component is bifurcated from the outside toward the inside of the semiconductor power module or two different components. The two parts are so structured that the parts are extended in a common direction. Control terminals (gate signal terminal and emitter signal terminal) are so arranged that a laminated portion of the control terminals is sandwiched between one and the other of the two parts to configure the semiconductor power module.
    Type: Application
    Filed: December 23, 2015
    Publication date: June 30, 2016
    Inventors: Keisuke HORIUCHI, Daisuke KAWASE, Masamitsu INABA, Katsuaki SAITO
  • Patent number: 9000601
    Abstract: The respective main electrodes of the semiconductor switching elements such as IGBTs, which are respectively mounted on the plurality of insulating boards, are electrically connected to each other via the conductor member. This configuration makes it possible to suppress the occurrence of the resonant voltage due to the junction capacity and the parasitic inductance of each semiconductor switching element.
    Type: Grant
    Filed: June 26, 2012
    Date of Patent: April 7, 2015
    Assignee: Hitachi Power Semiconductor Device, Ltd.
    Inventors: Katsunori Azuma, Kentaro Yasuda, Takahiro Fujita, Katsuaki Saito, Yoshihiko Koike, Michiaki Hiyoshi
  • Publication number: 20130001805
    Abstract: The respective main electrodes of the semiconductor switching elements such as IGBTs, which are respectively mounted on the plurality of insulating boards, are electrically connected to each other via the conductor member. This configuration makes it possible to suppress the occurrence of the resonant voltage due to the junction capacity and the parasitic inductance of each semiconductor switching element.
    Type: Application
    Filed: June 26, 2012
    Publication date: January 3, 2013
    Inventors: Katsunori AZUMA, Kentaro Yasuda, Takahiro Fujita, Katsuaki Saito, Yoshihiko Koike, Michiaki Hiyoshi
  • Patent number: 8304889
    Abstract: An elastic printed board is provided so that stress applied by the silicon gel is absorbed by the printed board. Further, the printed board is formed to be so narrow that the stress can escape. On the other hand, the wires on which a high voltage is applied are patterned on respective printed boards. This serves to prevent discharge through the surface of the same printed board serving as a current passage. This design makes it possible to hermetically close the power module, prevent intrusion of moisture or contamination as well as displacement, transformation and cracks of the cover plate.
    Type: Grant
    Filed: March 26, 2010
    Date of Patent: November 6, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Kazuhiro Oyama, Mutsuhiro Mori, Katsuaki Saito, Yoshihiko Koike
  • Patent number: 8283763
    Abstract: An elastic printed board is provided so that stress applied by the silicon gel is absorbed by the printed board. Further, the printed board is formed to be so narrow that the stress may be escaped. On the other hand, the wires on which a high voltage is applied are patterned on respective printed boards. This serves to prevent discharge through the surface of the same printed board served as current passage. This design makes it possible to hermetically close the power module, prevent intrusion of moisture or contamination as well as displacement, transformation and crack of the cover plate.
    Type: Grant
    Filed: June 13, 2007
    Date of Patent: October 9, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Kazuhiro Oyama, Mutsuhiro Mori, Katsuaki Saito, Yoshihiko Koike
  • Patent number: 8125090
    Abstract: Use of Pb-free solder has become essential due to the environmental problem. A power module is formed by soldering substrates with large areas. It is known that in Sn-3Ag-0.5Cu which hardly creeps and deforms with respect to large deformation followed by warpage of the substrate, life is significantly shortened with respect to the temperature cycle test, and the conventional module structure is in the situation having difficulty in securing high reliability. Thus, the present invention has an object to select compositions from which increase in life can be expected at a low strain rate. In Sn solder, by doping In by 3 to 7% and Ag by 2 to 4.5%, the effect of delaying crack development at a low strain rate is found out, and as a representative composition stable at a high temperature, Sn-3Ag-0.5Cu-5In is selected. Further, for enhancement of reliability, a method for partially coating a solder end portion with a resin is shown.
    Type: Grant
    Filed: July 27, 2010
    Date of Patent: February 28, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Tasao Soga, Daisuke Kawase, Kazuhiro Suzuki, Eiichi Morisaki, Katsuaki Saito, Hanae Shimokawa
  • Patent number: 8004075
    Abstract: Use of Pb-free solder has become essential due to the environmental problem. A power module is formed by soldering substrates with large areas. It is known that in Sn-3Ag-0.5Cu which hardly creeps and deforms with respect to large deformation followed by warpage of the substrate, life is significantly shortened with respect to the temperature cycle test, and the conventional module structure is in the situation having difficulty in securing high reliability. Thus, the present invention has an object to select compositions from which increase in life can be expected at a low strain rate. In Sn solder, by doping In by 3 to 7% and Ag by 2 to 4.5%, the effect of delaying crack development at a low strain rate is found out, and as a representative composition stable at a high temperature, Sn-3Ag-0.5Cu-5In is selected. Further, for enhancement of reliability, a method for partially coating a solder end portion with a resin is shown.
    Type: Grant
    Filed: April 24, 2007
    Date of Patent: August 23, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Tasao Soga, Daisuke Kawase, Kazuhiro Suzuki, Eiichi Morisaki, Katsuaki Saito, Hanae Shimokawa
  • Publication number: 20100289148
    Abstract: Use of Pb-free solder has become essential due to the environmental problem. A power module is formed by soldering substrates with large areas. It is known that in Sn-3Ag-0.5Cu which hardly creeps and deforms with respect to large deformation followed by warpage of the substrate, life is significantly shortened with respect to the temperature cycle test, and the conventional module structure is in the situation having difficulty in securing high reliability. Thus, the present invention has an object to select compositions from which increase in life can be expected at a low strain rate. In Sn solder, by doping In by 3 to 7% and Ag by 2 to 4.5%, the effect of delaying crack development at a low strain rate is found out, and as a representative composition stable at a high temperature, Sn-3Ag-0.5Cu-5In is selected. Further, for enhancement of reliability, a method for partially coating a solder end portion with a resin is shown.
    Type: Application
    Filed: July 27, 2010
    Publication date: November 18, 2010
    Inventors: Tasao SOGA, Daisuke Kawase, Kazuhiro Suzuki, Eiichi Morisaki, Katsuaki Saito, Hanae Shimokawa
  • Publication number: 20100176505
    Abstract: An elastic printed board is provided so that stress applied by the silicon gel is absorbed by the printed board. Further, the printed board is formed to be so narrow that the stress can escape. On the other hand, the wires on which a high voltage is applied are patterned on respective printed boards. This serves to prevent discharge through the surface of the same printed board serving as a current passage. This design makes it possible to hermetically close the power module, prevent intrusion of moisture or contamination as well as displacement, transformation and cracks of the cover plate.
    Type: Application
    Filed: March 26, 2010
    Publication date: July 15, 2010
    Inventors: Kazuhiro OYAMA, Mutsuhiro Mori, Katsuaki Saito, Yoshihiko Koike
  • Publication number: 20070290305
    Abstract: An elastic printed board is provided so that stress applied by the silicon gel is absorbed by the printed board. Further, the printed board is formed to be so narrow that the stress may be escaped. On the other hand, the wires on which a high voltage is applied are patterned on respective printed boards. This serves to prevent discharge through the surface of the same printed board served as current passage. This design makes it possible to hermetically close the power module, prevent intrusion of moisture or contamination as well as displacement, transformation and crack of the cover plate.
    Type: Application
    Filed: June 13, 2007
    Publication date: December 20, 2007
    Inventors: Kazuhiro Oyama, Mutsuhiro Mori, Katsuaki Saito, Yoshihiko Koike
  • Publication number: 20070246833
    Abstract: Use of Pb-free solder has become essential due to the environmental problem. A power module is formed by soldering substrates with large areas. It is known that in Sn-3Ag-0.5Cu which hardly creeps and deforms with respect to large deformation followed by warpage of the substrate, life is significantly shortened with respect to the temperature cycle test, and the conventional module structure is in the situation having difficulty in securing high reliability. Thus, the present invention has an object to select compositions from which increase in life can be expected at a low strain rate. In Sn solder, by doping In by 3 to 7% and Ag by 2 to 4.5%, the effect of delaying crack development at a low strain rate is found out, and as a representative composition stable at a high temperature, Sn-3Ag-0.5Cu-5In is selected. Further, for enhancement of reliability, a method for partially coating a solder end portion with a resin is shown.
    Type: Application
    Filed: April 24, 2007
    Publication date: October 25, 2007
    Inventors: Tasao Soga, Daisuke Kawase, Kazuhiro Suzuki, Eiichi Morisaki, Katsuaki Saito, Hanae Shimokawa
  • Publication number: 20060190198
    Abstract: An electric-information measurement/acquisition system comprising a sensor unit, a measurement unit, and an acquisition unit. The sensor unit includes sensors for detecting properties such as the voltage, current, temperature, and moisture,. The measurement unit includes: an A/D conversion unit for performing A/D conversion of the properties thus obtained at a predetermined first cycle; a first computing unit for performing computation at the predetermined first cycle and a predetermined second cycle so as to obtain intermediate data including the accumulated values of the averages of the properties including power-consumption data; and a transmission/reception unit for transmitting the intermediate data according to a request from the acquisition unit at a predetermined third cycle. The acquisition unit performs computation processing and correction processing for the intermediate data obtained from the multiple measurement units, thereby obtaining the properties thereof in a final format.
    Type: Application
    Filed: February 18, 2005
    Publication date: August 24, 2006
    Inventors: Tadashi Ishi, Katsuaki Saito
  • Patent number: 5883403
    Abstract: In a semiconductor device, such as a diode and thyristor, having at least one pn junction between a pair of main surfaces, a first main electrode formed on the surface of one of the main surfaces and a second main electrode formed on the surface of the other one of the main surfaces, a semiconductor lattice defect is formed such that its lattice defect density increases gradually in the direction from the first main electrode to the second main electrode. Since the distribution of the carrier density in the conduction state can be flattened, the reverse recovery charge can be reduced substantially without causing the ON-state voltage to increase.
    Type: Grant
    Filed: September 27, 1996
    Date of Patent: March 16, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Katsumi Ishikawa, Katsuaki Saito, Yutaka Sato, Atsuo Watanabe, Shuji Katoh, Naohiro Momma
  • Patent number: 5745336
    Abstract: A semiconductor integrated circuit apparatus according to the present invention has a capacitor formed in such a manner that a ferroelectric thin film is formed after a MOS transistor has been formed on a substrate thereof, a ferroelectric thin film made of, for example, PbZrTiO.sub.3 or SrTiO.sub.3 or the like is formed into a columnar shape to form electrodes positioned in direct contact with the side wall portions of said columnar ferroelectric thin film and the top portion is removed.
    Type: Grant
    Filed: April 6, 1995
    Date of Patent: April 28, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Katsuaki Saito, Michio Ohue, Takuya Fukuda, JaiHo Choi, Yukinobu Miyamoto
  • Patent number: 5710442
    Abstract: A semiconductor device sets an impurity density of a p base layer in a bevel end-face region to a density lower than that in an operating region and has a parasitic channel preventive region provided between the bevel end-face region and the operating region. Since the blocking-voltage and the current-carrying capacity can be adjusted independently from each other, the blocking voltage and the current-carrying capacity can be both improved.
    Type: Grant
    Filed: January 22, 1996
    Date of Patent: January 20, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Atsuo Watanabe, Katsuaki Saito
  • Patent number: 5434742
    Abstract: A semiconductor integrated circuit apparatus according to the present invention has a capacitor formed in such a manner that a ferroelectric thin film is formed after a MOS transistor has been formed on a substrate thereof, a ferroelectric thin film made of, for example, PbZrTiO.sub.3 or SrTiO.sub.3 or the like is formed into a columnar shape to form electrodes positioned in direct contact with the side wall portions of said columnar ferroelectric thin film, and the top portion is removed.
    Type: Grant
    Filed: December 23, 1992
    Date of Patent: July 18, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Katsuaki Saito, Michio Ohue, Takuya Fukuda, JaiHo Choi, Yukinobu Miyamoto
  • Patent number: 5347100
    Abstract: Disclosed are a semiconductor device comprising a semiconductor substrate, a first metal connection layers, a first substrate oxide layer having a specific form, and a second connection pattern layer; a process for producing the device; and a microwave plasma treatment apparatus having gas feed ports in a specific position. The highly reliable semiconductor devices can be produced at a high rate at high yields.
    Type: Grant
    Filed: March 26, 1992
    Date of Patent: September 13, 1994
    Assignees: Hitachi, Ltd., Hitachi Engineering & Services, Inc.
    Inventors: Takuya Fukuda, Michio Ohue, Fumiyuki Kanai, Atsuyoshi Koike, Katsuaki Saito, Kazuo Suzuki