Patents by Inventor Katsuaki Saito
Katsuaki Saito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240379830Abstract: A semiconductor device has both low conduction loss and low switching loss, and uniformity of heat generation during operation. The semiconductor device has high and low conduction regions in one semiconductor chip, and includes: in the low conduction region, a first carrier control gate connected to a first gate electrode, and a switching gate connected to a second gate electrode controllable independently of the first gate electrode; and in the high conduction region, a second carrier control gate connected to a third gate electrode. In the semiconductor device, of the first carrier control gate and the switching gate, the first carrier control gate is placed at an end portion of the low conduction region on a boundary side with the high conduction region, and a concentration of carriers that can be accumulated at conduction time is lower in the low conduction region than in the high conduction region.Type: ApplicationFiled: April 8, 2022Publication date: November 14, 2024Inventors: Tomoyuki MIYOSHI, Katsuaki SAITO, Tomoyasu FURUKAWA
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Publication number: 20240297592Abstract: Provided is a power semiconductor module comprising: a gate terminal to which a control signal is inputted; a reference potential terminal disposed adjacent to the gate terminal with a predetermined interval from the gate terminal; a main circuit wiring disposed in the vicinity of the reference potential terminal and the gate terminal; and an electromagnetic shield disposed between the gate terminal and the reference potential terminal to shield induction field generated by current flowing through the main circuit wiring. The present invention is also characterized in that: the electromagnetic shield is integrally formed with the gate terminal and/or the reference potential terminal; and, in a portion between the gate terminal and the reference potential terminal, a gap that is not shielded by the electromagnetic shield as seen from a direction in which a magnetic flux of the induction field intersects with the electromagnetic shield, is 1 mm or less.Type: ApplicationFiled: May 10, 2022Publication date: September 5, 2024Applicant: HITACHI POWER SEMICONDUCTOR DEVICE, LTD.Inventors: Taiga Arai, Daisuke Kawase, Akira Mima, Katsuaki Saito
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Patent number: 10781902Abstract: For a gear train GL including a drive gear 33 and an idler gear 34 engaged with each other and a lock gear 35, provided are a first drive means 3A configured to linearly drive the lock gear 35 in forward and backward directions, a second drive means 3B configured to rotationally drive the drive gear 33 in normal and reverse directions, and a controller C configured to control the both drive means 3A and 3B. The controller C starts driving the lock gear 35 at the time of an unlocking operation, from an engagement position toward the disengagement position through the first drive means 3A, and when the drive is started, the controller C drives the drive gear 33 into one of normal and reverse directions and into the other direction through the second drive means 3B with a polarity reversal in a predetermined cycles T1 and T2.Type: GrantFiled: March 29, 2018Date of Patent: September 22, 2020Assignee: SINFONIA TECHNOLOGY CO., LTD.Inventors: Masaharu Tsujimura, Katsuaki Saito
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Patent number: 10374414Abstract: A semiconductor power module with which it is possible to suppress the influence of noise given from a main terminal to a control terminal is provided. At least any one of main terminals (positive electrode terminal, negative electrode terminal, alternating current terminal) is so configured that the main terminal includes two parts extended in a common direction. The two parts are, for example, formed of a single component having such as a shape that the component is bifurcated from the outside toward the inside of the semiconductor power module or two different components. The two parts are so structured that the parts are extended in a common direction. Control terminals (gate signal terminal and emitter signal terminal) are so arranged that a laminated portion of the control terminals is sandwiched between one and the other of the two parts to configure the semiconductor power module.Type: GrantFiled: December 23, 2015Date of Patent: August 6, 2019Assignee: HITACHI POWER SEMICONDUCTOR DEVICE, LTD.Inventors: Keisuke Horiuchi, Daisuke Kawase, Masamitsu Inaba, Katsuaki Saito
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Publication number: 20180283512Abstract: For a gear train GL including a drive gear 33 and an idler gear 34 engaged with each other and a lock gear 35, provided are a first drive means 3A configured to linearly drive the lock gear 35 in forward and backward directions, a second drive means 3B configured to rotationally drive the drive gear 33 in normal and reverse directions, and a controller C configured to control the both drive means 3A and 3B. The controller C starts driving the lock gear 35 at the time of an unlocking operation, from an engagement position toward the disengagement position through the first drive means 3A, and when the drive is started, the controller C drives the drive gear 33 into one of normal and reverse directions and into the other direction through the second drive means 3B with a polarity reversal in a predetermined cycles T1 and T2.Type: ApplicationFiled: March 29, 2018Publication date: October 4, 2018Applicant: SINFONIA TECHNOLOGY CO., LTD.Inventors: Masaharu Tsujimura, Katsuaki Saito
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Publication number: 20160190915Abstract: A semiconductor power module with which it is possible to suppress the influence of noise given from a main terminal to a control terminal is provided. At least any one of main terminals (positive electrode terminal, negative electrode terminal, alternating current terminal) is so configured that the main terminal includes two parts extended in a common direction. The two parts are, for example, formed of a single component having such as a shape that the component is bifurcated from the outside toward the inside of the semiconductor power module or two different components. The two parts are so structured that the parts are extended in a common direction. Control terminals (gate signal terminal and emitter signal terminal) are so arranged that a laminated portion of the control terminals is sandwiched between one and the other of the two parts to configure the semiconductor power module.Type: ApplicationFiled: December 23, 2015Publication date: June 30, 2016Inventors: Keisuke HORIUCHI, Daisuke KAWASE, Masamitsu INABA, Katsuaki SAITO
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Patent number: 9000601Abstract: The respective main electrodes of the semiconductor switching elements such as IGBTs, which are respectively mounted on the plurality of insulating boards, are electrically connected to each other via the conductor member. This configuration makes it possible to suppress the occurrence of the resonant voltage due to the junction capacity and the parasitic inductance of each semiconductor switching element.Type: GrantFiled: June 26, 2012Date of Patent: April 7, 2015Assignee: Hitachi Power Semiconductor Device, Ltd.Inventors: Katsunori Azuma, Kentaro Yasuda, Takahiro Fujita, Katsuaki Saito, Yoshihiko Koike, Michiaki Hiyoshi
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Publication number: 20130001805Abstract: The respective main electrodes of the semiconductor switching elements such as IGBTs, which are respectively mounted on the plurality of insulating boards, are electrically connected to each other via the conductor member. This configuration makes it possible to suppress the occurrence of the resonant voltage due to the junction capacity and the parasitic inductance of each semiconductor switching element.Type: ApplicationFiled: June 26, 2012Publication date: January 3, 2013Inventors: Katsunori AZUMA, Kentaro Yasuda, Takahiro Fujita, Katsuaki Saito, Yoshihiko Koike, Michiaki Hiyoshi
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Patent number: 8304889Abstract: An elastic printed board is provided so that stress applied by the silicon gel is absorbed by the printed board. Further, the printed board is formed to be so narrow that the stress can escape. On the other hand, the wires on which a high voltage is applied are patterned on respective printed boards. This serves to prevent discharge through the surface of the same printed board serving as a current passage. This design makes it possible to hermetically close the power module, prevent intrusion of moisture or contamination as well as displacement, transformation and cracks of the cover plate.Type: GrantFiled: March 26, 2010Date of Patent: November 6, 2012Assignee: Hitachi, Ltd.Inventors: Kazuhiro Oyama, Mutsuhiro Mori, Katsuaki Saito, Yoshihiko Koike
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Patent number: 8283763Abstract: An elastic printed board is provided so that stress applied by the silicon gel is absorbed by the printed board. Further, the printed board is formed to be so narrow that the stress may be escaped. On the other hand, the wires on which a high voltage is applied are patterned on respective printed boards. This serves to prevent discharge through the surface of the same printed board served as current passage. This design makes it possible to hermetically close the power module, prevent intrusion of moisture or contamination as well as displacement, transformation and crack of the cover plate.Type: GrantFiled: June 13, 2007Date of Patent: October 9, 2012Assignee: Hitachi, Ltd.Inventors: Kazuhiro Oyama, Mutsuhiro Mori, Katsuaki Saito, Yoshihiko Koike
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Patent number: 8125090Abstract: Use of Pb-free solder has become essential due to the environmental problem. A power module is formed by soldering substrates with large areas. It is known that in Sn-3Ag-0.5Cu which hardly creeps and deforms with respect to large deformation followed by warpage of the substrate, life is significantly shortened with respect to the temperature cycle test, and the conventional module structure is in the situation having difficulty in securing high reliability. Thus, the present invention has an object to select compositions from which increase in life can be expected at a low strain rate. In Sn solder, by doping In by 3 to 7% and Ag by 2 to 4.5%, the effect of delaying crack development at a low strain rate is found out, and as a representative composition stable at a high temperature, Sn-3Ag-0.5Cu-5In is selected. Further, for enhancement of reliability, a method for partially coating a solder end portion with a resin is shown.Type: GrantFiled: July 27, 2010Date of Patent: February 28, 2012Assignee: Hitachi, Ltd.Inventors: Tasao Soga, Daisuke Kawase, Kazuhiro Suzuki, Eiichi Morisaki, Katsuaki Saito, Hanae Shimokawa
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Patent number: 8004075Abstract: Use of Pb-free solder has become essential due to the environmental problem. A power module is formed by soldering substrates with large areas. It is known that in Sn-3Ag-0.5Cu which hardly creeps and deforms with respect to large deformation followed by warpage of the substrate, life is significantly shortened with respect to the temperature cycle test, and the conventional module structure is in the situation having difficulty in securing high reliability. Thus, the present invention has an object to select compositions from which increase in life can be expected at a low strain rate. In Sn solder, by doping In by 3 to 7% and Ag by 2 to 4.5%, the effect of delaying crack development at a low strain rate is found out, and as a representative composition stable at a high temperature, Sn-3Ag-0.5Cu-5In is selected. Further, for enhancement of reliability, a method for partially coating a solder end portion with a resin is shown.Type: GrantFiled: April 24, 2007Date of Patent: August 23, 2011Assignee: Hitachi, Ltd.Inventors: Tasao Soga, Daisuke Kawase, Kazuhiro Suzuki, Eiichi Morisaki, Katsuaki Saito, Hanae Shimokawa
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Publication number: 20100289148Abstract: Use of Pb-free solder has become essential due to the environmental problem. A power module is formed by soldering substrates with large areas. It is known that in Sn-3Ag-0.5Cu which hardly creeps and deforms with respect to large deformation followed by warpage of the substrate, life is significantly shortened with respect to the temperature cycle test, and the conventional module structure is in the situation having difficulty in securing high reliability. Thus, the present invention has an object to select compositions from which increase in life can be expected at a low strain rate. In Sn solder, by doping In by 3 to 7% and Ag by 2 to 4.5%, the effect of delaying crack development at a low strain rate is found out, and as a representative composition stable at a high temperature, Sn-3Ag-0.5Cu-5In is selected. Further, for enhancement of reliability, a method for partially coating a solder end portion with a resin is shown.Type: ApplicationFiled: July 27, 2010Publication date: November 18, 2010Inventors: Tasao SOGA, Daisuke Kawase, Kazuhiro Suzuki, Eiichi Morisaki, Katsuaki Saito, Hanae Shimokawa
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Publication number: 20100176505Abstract: An elastic printed board is provided so that stress applied by the silicon gel is absorbed by the printed board. Further, the printed board is formed to be so narrow that the stress can escape. On the other hand, the wires on which a high voltage is applied are patterned on respective printed boards. This serves to prevent discharge through the surface of the same printed board serving as a current passage. This design makes it possible to hermetically close the power module, prevent intrusion of moisture or contamination as well as displacement, transformation and cracks of the cover plate.Type: ApplicationFiled: March 26, 2010Publication date: July 15, 2010Inventors: Kazuhiro OYAMA, Mutsuhiro Mori, Katsuaki Saito, Yoshihiko Koike
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Publication number: 20070290305Abstract: An elastic printed board is provided so that stress applied by the silicon gel is absorbed by the printed board. Further, the printed board is formed to be so narrow that the stress may be escaped. On the other hand, the wires on which a high voltage is applied are patterned on respective printed boards. This serves to prevent discharge through the surface of the same printed board served as current passage. This design makes it possible to hermetically close the power module, prevent intrusion of moisture or contamination as well as displacement, transformation and crack of the cover plate.Type: ApplicationFiled: June 13, 2007Publication date: December 20, 2007Inventors: Kazuhiro Oyama, Mutsuhiro Mori, Katsuaki Saito, Yoshihiko Koike
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Publication number: 20070246833Abstract: Use of Pb-free solder has become essential due to the environmental problem. A power module is formed by soldering substrates with large areas. It is known that in Sn-3Ag-0.5Cu which hardly creeps and deforms with respect to large deformation followed by warpage of the substrate, life is significantly shortened with respect to the temperature cycle test, and the conventional module structure is in the situation having difficulty in securing high reliability. Thus, the present invention has an object to select compositions from which increase in life can be expected at a low strain rate. In Sn solder, by doping In by 3 to 7% and Ag by 2 to 4.5%, the effect of delaying crack development at a low strain rate is found out, and as a representative composition stable at a high temperature, Sn-3Ag-0.5Cu-5In is selected. Further, for enhancement of reliability, a method for partially coating a solder end portion with a resin is shown.Type: ApplicationFiled: April 24, 2007Publication date: October 25, 2007Inventors: Tasao Soga, Daisuke Kawase, Kazuhiro Suzuki, Eiichi Morisaki, Katsuaki Saito, Hanae Shimokawa
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Publication number: 20060190198Abstract: An electric-information measurement/acquisition system comprising a sensor unit, a measurement unit, and an acquisition unit. The sensor unit includes sensors for detecting properties such as the voltage, current, temperature, and moisture,. The measurement unit includes: an A/D conversion unit for performing A/D conversion of the properties thus obtained at a predetermined first cycle; a first computing unit for performing computation at the predetermined first cycle and a predetermined second cycle so as to obtain intermediate data including the accumulated values of the averages of the properties including power-consumption data; and a transmission/reception unit for transmitting the intermediate data according to a request from the acquisition unit at a predetermined third cycle. The acquisition unit performs computation processing and correction processing for the intermediate data obtained from the multiple measurement units, thereby obtaining the properties thereof in a final format.Type: ApplicationFiled: February 18, 2005Publication date: August 24, 2006Inventors: Tadashi Ishi, Katsuaki Saito
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Patent number: 5883403Abstract: In a semiconductor device, such as a diode and thyristor, having at least one pn junction between a pair of main surfaces, a first main electrode formed on the surface of one of the main surfaces and a second main electrode formed on the surface of the other one of the main surfaces, a semiconductor lattice defect is formed such that its lattice defect density increases gradually in the direction from the first main electrode to the second main electrode. Since the distribution of the carrier density in the conduction state can be flattened, the reverse recovery charge can be reduced substantially without causing the ON-state voltage to increase.Type: GrantFiled: September 27, 1996Date of Patent: March 16, 1999Assignee: Hitachi, Ltd.Inventors: Katsumi Ishikawa, Katsuaki Saito, Yutaka Sato, Atsuo Watanabe, Shuji Katoh, Naohiro Momma
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Patent number: 5745336Abstract: A semiconductor integrated circuit apparatus according to the present invention has a capacitor formed in such a manner that a ferroelectric thin film is formed after a MOS transistor has been formed on a substrate thereof, a ferroelectric thin film made of, for example, PbZrTiO.sub.3 or SrTiO.sub.3 or the like is formed into a columnar shape to form electrodes positioned in direct contact with the side wall portions of said columnar ferroelectric thin film and the top portion is removed.Type: GrantFiled: April 6, 1995Date of Patent: April 28, 1998Assignee: Hitachi, Ltd.Inventors: Katsuaki Saito, Michio Ohue, Takuya Fukuda, JaiHo Choi, Yukinobu Miyamoto
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Patent number: 5710442Abstract: A semiconductor device sets an impurity density of a p base layer in a bevel end-face region to a density lower than that in an operating region and has a parasitic channel preventive region provided between the bevel end-face region and the operating region. Since the blocking-voltage and the current-carrying capacity can be adjusted independently from each other, the blocking voltage and the current-carrying capacity can be both improved.Type: GrantFiled: January 22, 1996Date of Patent: January 20, 1998Assignee: Hitachi, Ltd.Inventors: Atsuo Watanabe, Katsuaki Saito