Abstract: A semiconductor device includes a conductive film containing molybdenum and a metal element. The metal element has a melting point lower than the melting point of molybdenum and forms a complete solid solution with molybdenum. The metal element as a material for composing the conductive film is at least one selected from the group consisting of, for example, titanium, vanadium, and niobium.

Abstract: An information processing apparatus detecting presence or absence of abnormality of a vacuum pump derived from a product produced within a target vacuum pump, including: a determination unit configured to determine a normal variation range or a normal time variation behavior of a target state quantity which is a state quantity varying depending on a load of gas flowing into the vacuum pump, based on at least one of past target state quantities of the target vacuum pump or another vacuum pump; and a comparison unit configured to compare a current target state quantity of the target vacuum pump with the normal variation range or the normal time variation behavior and output the comparison result.

Abstract: A radiation-sensitive resin composition contains: a first polymer having a first structural unit including a partial structure obtained by substituting a hydrogen atom of a carboxy group or of a phenolic hydroxy group with an acid-labile group represented by formula (1); and a compound including: a monovalent radiation-sensitive onium cation moiety including an aromatic ring structure which includes a fluorine atom or a fluorine atom-containing group; and a monovalent organic acid anion moiety. Ar1 represents a group obtained by removing one hydrogen atom from a substituted or unsubstituted aromatic ring structure having 5 to 30 ring atoms; R 1 and R2 each independently represent a substituted or unsubstituted monovalent aliphatic hydrocarbon group having 1 to 10 carbon atoms; and * denotes a site bonding to an ethereal oxygen atom in the carboxy group or an oxygen atom in the phenolic hydroxy group.

Abstract: A semiconductor storage device includes a first region including a level shifter, a second region including a level shifter, a power input pad, and an internal power generation circuit configured to generate an internal power supply voltage using a first power supply voltage supplied through the power input pad and supply the internal power supply voltage to the first and second regions. The internal power generation circuit separately transmits a first signal to the level shifter of the first region for triggering a start of a first operation of the first region and a second signal to the level shifter of the second region for triggering a start of a second operation of the second region.

Abstract: In one embodiment, a semiconductor storage device includes a string that has one end electrically connected to a bit line, and another end electrically connected to a source line, and includes a plurality of memory cells. An operation of writing data to each of a plurality of adjacent first memory cells among the plurality of memory cells is sequentially performed in a direction from a first memory cell on a side of the source line to a first memory cell on a side of the bit line. An operation of reading data from each of the plurality of adjacent first memory cells is performed to allow a current to flow through the string in a first direction from the source line to the bit line.

Abstract: A change in electrical characteristics of a semiconductor device including an interlayer insulating film over a transistor including an oxide semiconductor as a semiconductor film is suppressed. The structure includes a first insulating film which includes a void portion in a step region formed by a source electrode and a drain electrode over the semiconductor film and contains silicon oxide as a component, and a second insulating film containing silicon nitride, which is provided in contact with the first insulating film to cover the void portion in the first insulating film. The structure can prevent the void portion generated in the first insulating film from expanding outward.

Abstract: A semiconductor device includes: a first output transistor and a second output transistor configured to be connected between a first terminal and second terminal; an active clamp circuit configured to be connected to a first control terminal of the first output transistor to limit a terminal-to-terminal voltage appearing between the first and second terminals to a clamp voltage or less; a first variable resistive element provided between a node configured to be fed with a control signal and the first control terminal; a second variable resistive element provided between the node and a second control terminal of the second output transistor; and a turn-off circuit configured to be connected to a connection node between the second variable resistive element and the second control terminal so as to be able to turn the second output transistor off.

Abstract: Provided is a shopping cart capable of simplifying equipment of a storage area of the shopping cart. A shopping cart allowed to be nested in a front-rear direction, including: a cart body; a battery configured to supply power to an electronic device attached to the cart body and displayed commodity information read by a reading device; a power receiving portion provided on a front side of the cart body and configured to be electrically connectable to an external power supply; and a power transmitting portion provided on a rear surface side of the power receiving portion and configured to supply power to a power receiving portion of another shopping cart nested in the shopping cart. Each of the power receiving portion and the power transmitting portion is provided with a magnet configured for holding a relative position.

Abstract: A semiconductor memory device includes a first memory cell transistor, a first bit line electrically coupled to the first memory cell transistor, a first sense amplifier, and a first latch circuit. The first sense amplifier includes a first node coupled to the first bit line, a first transistor including one end electrically coupled to the first latch circuit, a second node coupled to a gate of the first transistor, and a second transistor coupled between the first and second nodes. The second transistor is in an ON state during an operation of transferring a charge from the first bit line to the first and second nodes in accordance with data of the first memory cell transistor. The second transistor is in an OFF state during an operation of transferring data of the second node to the first latch circuit.

Abstract: An all-solid-state battery includes a case, a battery element, and a restraint component. The case accommodates the battery element. The battery element includes an electrode part and a resin part. The resin part covers at least a part of a side face of the electrode part. The restraint component applies a first pressure to the electrode part. The restraint component applies a second pressure to the resin part. The ratio of the second pressure to the first pressure is from 1.5 to 18.

Abstract: An information processing apparatus detecting presence or absence of abnormality of a vacuum pump derived from a product produced within a target vacuum pump, including: a determination unit configured to determine a normal variation range or a normal time variation behavior of a target state quantity which is a state quantity varying depending on a load of gas flowing into the vacuum pump, based on at least one of past target state quantities of the target vacuum pump or another vacuum pump; and a comparison unit configured to compare a current target state quantity of the target vacuum pump with the normal variation range or the normal time variation behavior and output the comparison result.

Abstract: A semiconductor substrate includes a heterogeneous substrate, a mask layer having an opening portion and a mask portion, a seed portion overlapping the opening portion, and a semiconductor layer including a GaN-based semiconductor and disposed on the seed portion and the mask portion. An upper surface of an effective portion of the semiconductor layer includes at least one low-level defective region with a size of 10 ?m in a first direction along a width direction of the opening portion and 10 ?m in a second direction orthogonal to the first direction, and a line defect is not measured by a CL method in the low-level defective region.

Abstract: A biosample processing apparatus of an embodiment includes a sample supply part, a first collection part, a separation part, and a second collection part. The sample supply part is connected to one end of a tubular flow path and supplies a first sample containing components extracted from a subject to the flow path. The first collection part is provided on the flow path and collects target cells to be cultured from the first sample supplied to the flow path. The separation part is provided downstream of the first collection part on the flow path and separates a blood plasma component or a blood serum component as a second sample from the first sample from which the target cells have been collected by the first collection part. The second collection part is connected to another end of the flow path and collects the second sample separated by the separation part.

Abstract: A cell culture apparatus of an embodiment includes a culture medium housing part, a cell housing part, a discharge path, a culture part, and a movable wall. The culture medium housing part houses a culture medium. The cell housing part houses the cells. The discharge path is the path of the waste liquid. The culture part has a hollow tubular shape with holes provided at both ends. The culture medium housing part, the cell housing part, and the discharge path are connected to one of the holes in a switchable manner. The movable wall is arranged in a slidable manner along an inner peripheral face of the culture part. The cell culture apparatus performs sucking from at least either the culture medium housing part or the cell housing part into the culture part and discharge from inside the culture part to the discharge path.

Abstract: A semiconductor device with a high on-state current is provided. The semiconductor device includes a first oxide, a second oxide over the first oxide, a third oxide over the second oxide, a first insulator over the third oxide, a conductor over the first insulator, a second insulator in contact with the second oxide and the third oxide, and a third insulator over the second insulator; the second oxide includes first region to fifth regions; the resistance of the first region and the resistance of the second region are lower than the resistance of the third region; the resistance of the fourth region and the resistance of the fifth region are lower than the resistance of the third region and higher than the resistance of the first region and the resistance of the second region; and the conductor is provided over the third region, the fourth region, and the fifth region to overlap with the third region, the fourth region, and the fifth region.

Abstract: Provided is a shopping cart capable of simplifying equipment of a storage area of the shopping cart. A shopping cart allowed to be nested in a front-rear direction, includes: a cart body; a battery configured to supply power to an electronic device attached to the cart body and displayed commodity information read by a reading device; power receiving units and provided on a front side of the cart body and configured to be electrically connectable to an external power supply device; and power transmitting units and provided on a rear surface side of the power receiving units and configured to supply power to a power receiving units and of another shopping cart nested in the shopping cart.

Abstract: A patterned pressure-sensitive adhesive tape includes a pressure-sensitive adhesive layer. The pressure-sensitive adhesive layer is formed by a pressure-sensitive adhesive composition for patterned pressure-sensitive adhesive tape. An elongational viscosity of the pressure-sensitive adhesive composition measured at 30° C. is 1,000 mPa·s or greater and 650,000 mPa·s or less, or a Trouton's ratio thereof measured at 30° C. is 8 or greater and 400 or less. The pressure-sensitive adhesive layer has two or more pressure-sensitive adhesive portions (B) and a non-pressure-sensitive adhesive portion region having no pressure-sensitive adhesive portions (B) between the two or more pressure-sensitive adhesive portions (B). The non-pressure-sensitive adhesive portion region is patterned to lead to an outer periphery of a sheet plane.

Abstract: A hydraulic excavator is provided which can suppress the fuel consumption amount and improve the work efficiency by reducing the hydraulic pressure loss generated when a plurality of hydraulic actuators different in load are operated simultaneously.

Abstract: A sheet-shaped cooked rice forming jig includes: a forming frame for forming a sheet-shaped cooked rice, the sheet-shaped cooked rice being formed by packing a cooked rice in the forming frame; and a leveling spatula for leveling the cooked rice packed in the forming frame into a sheet shape. The forming frame is a flat-plate-like member having a predetermined thickness where upper and lower surfaces of the forming frame are formed into a flat surface. The forming frame is formed in a window shape in an endless manner so as to form a cooked rice packing portion in a penetrating manner inside the forming frame. The cooked rice is packed into the cooked rice packing portion, and the leveling spatula is formed of: a grip portion; and a spatula body portion extending from a distal end of the grip portion and having a flat shape.

Abstract: A semiconductor storage device includes a bit line, a select gate line, a sense amplifier circuit, a first transistor between the bit line and the sense amplifier circuit, and a second transistor between the bit line and a voltage generation circuit. In a first period of a program operation, the first transistor is turned OFF and the second transistor is turned ON, and a voltage of the first bit line is at a first voltage and a voltage of the select gate line is at a second voltage. In a second period of the program operation, the first transistor is turned ON and the second transistor is turned OFF, and a voltage of the first bit line is at a third voltage less than the first voltage and a voltage of the select gate line is at a fourth voltage greater than the second voltage.