Abstract: A DC converter with a halt mode setting is disclosed for preventing the occurrence of over-current while alleviating the increase in the size of circuits, along with a method for setting up such a halt mode. The DC converter includes a semiconductor switch, a clock generator for outputting a clock signal to a gate of the semiconductor switch to be utilized for controlling an on/off time of the semiconductor switch such that a predetermined power is output from the generator, and a drive circuit for switching the semiconductor switch to the continuous-on state according to a halt mode setting requirement regardless of the clock signal, when the semiconductor switch, normally repeating on/off operations responsive to the clock signal, is in its off-state.

Abstract: A DC converter with a halt mode setting is disclosed for preventing the occurrence of over-current while alleviating the increase in the size of circuits, along with a method for setting up such a halt mode. The DC converter includes a semiconductor switch, a clock generator for outputting a clock signal to a gate of the semiconductor switch to be utilized for controlling an on/off time of the semiconductor switch such that a predetermined power is output from the generator, and a drive circuit for switching the semiconductor switch to the continuous-on state according to a halt mode setting requirement regardless of the clock signal, when the semiconductor switch, normally repeating on/off operations responsive to the clock signal, is in its off-state.

Abstract: A DC converter with a halt mode setting is disclosed for preventing the occurrence of over-current while alleviating the increase in the size of circuits, along with a method for setting up such a halt mode. The DC converter includes a semiconductor switch, a clock generator for outputting a clock signal to a gate of the semiconductor switch to be utilized for controlling an on/off time of the semiconductor switch such that a predetermined power is output from the generator, and a drive circuit for switching the semiconductor switch to the continuous-on state according to a halt mode setting requirement regardless of the clock signal, when the semiconductor switch, normally repeating on/off operations responsive to the clock signal, is in its off-state.

Abstract: A method and apparatus of detecting a connection status of a digital video apparatus to a peripheral apparatus includes a digital video encoder configured to receive a digital video signal, and convert and output the digital video signal into an analog video signal, and a determination circuit configured to detect a voltage level of a horizontal synchronization signal of the analog video signal in a vertical blanking time determined by vertical synchronization signals, and determine whether the digital video apparatus is connected to a peripheral apparatus based on a detection result of the voltage of the horizontal synchronization signal of the analog video signal.

Abstract: A DC converter with a halt mode setting is disclosed for preventing the occurrence of over-current while alleviating the increase in the size of circuits, along with a method for setting up such a halt mode. The DC converter includes a semiconductor switch, a clock generator for outputting a clock signal to a gate of the semiconductor switch to be utilized for controlling an on/off time of the semiconductor switch such that a predetermined power is output from the generator, and a drive circuit for switching the semiconductor switch to the continuous-on state according to a halt mode setting requirement regardless of the clock signal, when the semiconductor switch, normally repeating on/off operations responsive to the clock signal, is in its off-state.

Abstract: A DC converter with a halt mode setting is disclosed for preventing the occurrence of over-current while alleviating the increase in the size of circuits, along with a method for setting up such a halt mode. The DC converter includes a semiconductor switch, a clock generator for outputting a clock signal to a gate of the semiconductor switch to be utilized for controlling an on/off time of the semiconductor switch such that a predetermined power is output from the generator, and a drive circuit for switching the semiconductor switch to the continuous-on state according to a halt mode setting requirement regardless of the clock signal, when the semiconductor switch, normally repeating on/off operations responsive to the clock signal, is in its off-state.

Abstract: An amplifying circuit includes a battery power source, a regulator that regulates an output of the battery power source and generates a reference voltage, and a signal ground generating device that generates and outputs a signal ground by changing the reference voltage in accordance with deterioration detected from the battery power source. An operational amplifier is provided to amplify and output a signal having prescribed waveform to be input to a speaker. The operational amplifier uses a battery power source as a driving power source of its own. The signal ground is positioned at a center of vibration amplitude of the waveform.

Abstract: A DC converter with a halt mode setting is disclosed for preventing the occurrence of over-current while alleviating the increase in the size of circuits, along with a method for setting up such a halt mode. The DC converter includes a semiconductor switch, a clock generator for outputting a clock signal to a gate of the semiconductor switch to be utilized for controlling an on/off time of the semiconductor switch such that a predetermined power is output from the generator, and a drive circuit for switching the semiconductor switch to the continuous-on state according to a halt mode setting requirement regardless of the clock signal, when the semiconductor switch, normally repeating on/off operations responsive to the clock signal, is in its off-state.

Abstract: A DC converter with a halt mode setting is disclosed for preventing the occurrence of over-current while alleviating the increase in the size of circuits, along with a method for setting up such a halt mode. The DC converter includes a semiconductor switch, a clock generator for outputting a clock signal to a gate of the semiconductor switch to be utilized for controlling an on/off time of the semiconductor switch such that a predetermined power is output from the generator, and a drive circuit for switching the semiconductor switch to the continuous-on state according to a halt mode setting requirement regardless of the clock signal, when the semiconductor switch, normally repeating on/off operations responsive to the clock signal, is in its off-state.

Abstract: A DC converter with a halt mode setting is disclosed for preventing the occurrence of over-current while alleviating the increase in the size of circuits, along with a method for setting up such a halt mode. The DC converter includes a semiconductor switch, a clock generator for outputting a clock signal to a gate of the semiconductor switch to be utilized for controlling an on/off time of the semiconductor switch such that a predetermined power is output from the generator, and a drive circuit for switching the semiconductor switch to the continuous-on state according to a halt mode setting requirement regardless of the clock signal, when the semiconductor switch, normally repeating on/off operations responsive to the clock signal, is in its off-state.

Abstract: A DC converter with a halt mode setting is disclosed for preventing the occurrence of over-current while alleviating the increase in the size of circuits, along with a method for setting up such a halt mode. The DC converter includes a semiconductor switch, a clock generator for outputting a clock signal to a gate of the semiconductor switch to be utilized for controlling an on/off time of the semiconductor switch such that a predetermined power is output from the generator, and a drive circuit for switching the semiconductor switch to the continuous-on state according to a halt mode setting requirement regardless of the clock signal, when the semiconductor switch, normally repeating on/off operations responsive to the clock signal, is in its off-state.

Abstract: A method and apparatus of detecting a connection status of a digital video apparatus to a peripheral apparatus includes a digital video encoder configured to receive a digital video signal, and convert and output the digital video signal into an analog video signal, and a determination circuit configured to detect a voltage level of a horizontal synchronization signal of the analog video signal in a vertical blanking time determined by vertical synchronization signals, and determine whether the digital video apparatus is connected to a peripheral apparatus based on a detection result of the voltage of the horizontal synchronization signal of the analog video signal.

Abstract: An amplifying circuit includes a battery power source, a regulator that regulates an output of the battery power source and generates a reference voltage, and a signal ground generating device that generates and outputs a signal ground by changing the reference voltage in accordance with deterioration detected from the battery power source. An operational amplifier is provided to amplify and output a signal having prescribed waveform to be input to a speaker. The operational amplifier uses a battery power source as a driving power source of its own. The signal ground is positioned at a center of vibration amplitude of the waveform.

Abstract: A DC converter with a halt mode setting is disclosed for preventing the occurrence of over-current while alleviating the increase in the size of circuits, along with a method for setting up such a halt mode. The DC converter includes a semiconductor switch, a clock generator for outputting a clock signal to a gate of the semiconductor switch to be utilized for controlling an on/off time of the semiconductor switch such that a predetermined power is output from the generator, and a drive circuit for switching the semiconductor switch to the continuous-on state according to a halt mode setting requirement regardless of the clock signal, when the semiconductor switch, normally repeating on/off operations responsive to the clock signal, is in its off-state.

Abstract: In an electronic still camera, image data obtained by a camera image pickup section are transmitted to an image data compression/extension circuit and are coded by this circuit. The coded image data are recorded to a FIFO circuit. The image data are then DMA-transferred to a memory card by a DMA controller within a memory card interface (I/F) and are recorded to the memory card. When the image data are regenerated, the image data are DMA-transferred in a reverse direction. In another camera, image data are outputted from a charge coupled device (CCD) and are converted to a digital signal. Sound data are outputted from a microphone and are converted to a digital signal. File header information is constructed by the image and sound data and is stored to a RAM of a memory card interface in advance. The file header information is recorded to a memory card by a direct memory access (DMA) control section.

Abstract: An electronic still camera which photographs an object and outputs image data. An image data coding device codes the image data. The coded image data is recorded to a recording medium. Sound data can also be converted to an electric signal and the sound data can be coded, converted to an electric signal, and then recorded to the recording media. A rearrangeable unused region of the recording media can be used as a work area for a file control work.

Abstract: In an electronic still camera, image data obtained by a camera image pickup section are transmitted to an image data compression/extension circuit and are coded by this circuit. The coded image data are recorded to a FIFO circuit. The image data are then DMA-transferred to a memory card by a DMA controller within a memory card interface (I/F) and are recorded to the memory card. When the image data are regenerated, the image data are DMA-transferred in a reverse direction. In another camera, image data are outputted from a charge coupled device (CCD) and are converted to a digital signal. Sound data are outputted from a microphone and are converted to a digital signal. File header information is constructed by the image and sound data and is stored to a RAM of a memory card interface in advance. The file header information is recorded to a memory card by a direct memory access (DMA) control section.

Abstract: In an electronic still camera, image data obtained by a camera image pickup section are transmitted to an image data compression/extension circuit and are coded by this circuit. The coded image data are recorded to a FIFO circuit. The image data are then DMA-transferred to a memory card by a DMA controller within a memory card interface (I/F) and are recorded to the memory card. When the image data are regenerated, the image data are DMA-transferred in a reverse direction. In another camera, image data are outputted from a charge coupled device (CCD) and are converted to a digital signal. Sound data are outputted from a microphone and are converted to a digital signal. File header information is constructed by the image and sound data and is stored to a RAM of a memory card interface in advance. The file header information is recorded to a memory card by a direct memory access (DMA) control section.

Abstract: In an electronic still camera, image data obtained by a camera image pickup section are transmitted to an image data compression/extension circuit and are coded by this circuit. The coded image data are recorded to a FIFO circuit. The image data are then DMA-transferred to a memory card by a DMA controller within a memory card interface (I/F) and are recorded to the memory card. When the image data are regenerated, the image data are DMA-transferred in a reverse direction.

Abstract: A digital still video camera including a camera processor which processes image data of a subject, a recording processor which generates recording data based on the processed image data, a recording controller which controls recording of the recording data to a recording medium, a memory which stores image data processed by the camera processor and recording data recorded in the recording medium, a control device which controls the camera processor, the recording processor, and the recording controller, and an evacuating/writing device which interrupts control by the control device and evacuates/writes the recorded recording data between the recording medium and the memory.