Patents by Inventor Katsuhiko Takeuchi

Katsuhiko Takeuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230282721
    Abstract: Fluctuation and deterioration of characteristics of a semiconductor device are reduced. The semiconductor device includes a field effect transistor mounted on a semiconductor base.
    Type: Application
    Filed: May 26, 2021
    Publication date: September 7, 2023
    Inventors: YUKI YANAGISAWA, KATSUHIKO TAKEUCHI
  • Publication number: 20230261099
    Abstract: A semiconductor device including: a channel layer; a barrier layer; a source electrode and a drain electrode; a gate electrode; a side surface opening region; and a low-Ns region. The channel layer includes a first nitride semiconductor. The barrier layer includes a second nitride semiconductor. The barrier layer is provided on the channel layer. The source electrode and the drain electrode are provided above the barrier layer. The gate electrode is provided above the barrier layer between the source electrode and the drain electrode. The side surface opening region is at least provided on one of side surfaces of the gate electrode between the source electrode or the drain electrode and the gate electrode. The low-Ns region is provided in the channel layer in correspondence with a planar region provided with the gate electrode and the side surface opening region. The low-Ns region has lower carrier density than carrier density of another region of the channel layer.
    Type: Application
    Filed: June 18, 2021
    Publication date: August 17, 2023
    Inventors: KAZUKI KISHIDA, KATSUHIKO TAKEUCHI
  • Publication number: 20230212110
    Abstract: A method for producing a carbamic acid salt, including contacting a carbon dioxide-containing mixed gas having a partial pressure of carbon dioxide of 0.001 atm or more and less than 1 atm with an amino group-containing organic compound in the presence of a base in at least one organic solvent selected from the group consisting of an organic solvent having 2 or more and 8 or less carbon atoms, and a method for producing a carbamic acid ester or a urea derivative using the carbamic acid salt.
    Type: Application
    Filed: June 3, 2021
    Publication date: July 6, 2023
    Applicants: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY, TOSOH CORPORATION
    Inventors: Katsuhiko TAKEUCHI, Kazuhiro MATSUMOTO, Norihisa FUKAYA, Hiroki KOIZUMI, Jun-Chul CHOI, Masahito UCHIDA, Seiji MATSUMOTO, Satoshi HAMURA
  • Patent number: 11682720
    Abstract: [Overview] [Problem to be Solved] To provide a switching transistor and a semiconductor module having lower distortion generated in a signal. [Solution] A switching transistor including: a channel layer including a compound semiconductor and having sheet electron density equal to or higher than 1.7×1013 cm?2; a barrier layer formed on the channel layer by using a compound semiconductor that is of a different type from the channel layer; a gate electrode provided on the barrier layer; and a source electrode and a drain electrode provided on the barrier layer with the gate electrode interposed between the source electrode and the drain electrode.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: June 20, 2023
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Satoshi Taniguchi, Masashi Yanagita, Katsuhiko Takeuchi, Shigeru Kanematsu, Takanori Higashi
  • Publication number: 20230178612
    Abstract: A semiconductor unit includes: a barrier layer including a first compound semiconductor; a channel layer including a second compound semiconductor, and bonded to the barrier layer at a first face; an insulation layer provided on a second face, of the barrier layer, that is on an opposite side of the first face, and having an opening section that exposes the barrier layer; a gate electrode provided to bury the opening section; a source electrode and a drain electrode that are provided on the second face of the barrier layer on both sides of the gate electrode with the gate electrode being interposed; and a material layer including a metal material or a semiconductor material, and provided in contact with the second face of the barrier layer between the gate electrode and the drain electrode.
    Type: Application
    Filed: March 31, 2021
    Publication date: June 8, 2023
    Inventor: KATSUHIKO TAKEUCHI
  • Publication number: 20230014905
    Abstract: The on-resistance of each of field effect transistors having different planar sizes is reduced. A semiconductor device includes first and second field effect transistors mounted on a semiconductor substrate and an insulating layer provided on a main surface of the semiconductor substrate. Here, each of the first and second field effect transistors includes a pair of main electrodes which are separated from each other and provided on the main surface of the semiconductor substrate, a cavity part which is provided in the insulating layer between the pair of main electrodes, and a gate electrode which has a head part positioned on the insulating layer and a body part that penetrates the insulating layer from the head part and protrudes toward the cavity part and in which the head part is wider than the body part. Here, the width of the cavity part of the second field effect transistor is different from the width of the cavity part of the first field effect transistor.
    Type: Application
    Filed: October 29, 2020
    Publication date: January 19, 2023
    Inventors: KATSUHIKO TAKEUCHI, KEITA TAKAHASHI
  • Publication number: 20220399329
    Abstract: A semiconductor device includes: a semiconductor material layer forming a channel layer; a pair of source/drain electrodes formed on the semiconductor material layer; and a gate electrode arranged between the pair of source/drain electrodes and formed on the semiconductor material layer via a gate insulating film, wherein a connection path using a capacitor in which an insulating film formed in the same layer as the gate insulating film is sandwiched by a pair of electrodes and that undergoes dielectric breakdown at a voltage lower than a dielectric breakdown voltage of the gate insulating film is formed between at least one of the pair of source/drain electrodes and the gate electrode.
    Type: Application
    Filed: October 15, 2020
    Publication date: December 15, 2022
    Inventors: SHINYA MORITA, KATSUHIKO TAKEUCHI
  • Publication number: 20220352362
    Abstract: A semiconductor device includes: a semiconductor material layer forming a channel layer; a pair of source/drain electrodes formed on the semiconductor material layer; and a gate electrode arranged between the pair of source/drain electrodes and formed on the semiconductor material layer, at least one of the pair of source/drain electrodes and the gate electrode being connected via a resistive element.
    Type: Application
    Filed: October 15, 2020
    Publication date: November 3, 2022
    Inventor: KATSUHIKO TAKEUCHI
  • Publication number: 20220278210
    Abstract: A semiconductor device includes: a semiconductor layer including a channel layer; a contact region provided at a predetermined size in a thickness direction of the semiconductor layer, and having an impurity concentration that is higher than an impurity concentration of the surrounding semiconductor layer; a gate electrode facing the channel layer, and provided on the semiconductor layer and spaced from the contact region; and an electrode that is in contact with the semiconductor layer and electrically coupled to the channel layer via the contact region, and extending more on at least the gate electrode side than the contact region.
    Type: Application
    Filed: July 17, 2020
    Publication date: September 1, 2022
    Inventors: Katsuhiko Takeuchi, Masashi Yanagita
  • Patent number: 11127743
    Abstract: A transistor including a carrier transit layer that includes a compound semiconductor and a carrier supply layer in contact with the carrier transit layer. The carrier supply layer includes a compound semiconductor of a different type from the carrier transit layer. The transistor includes a gate electrode provided on the carrier supply layer, and a source electrode and a drain electrode provided on another surface of the carrier transit layer that is opposite to one surface on which the carrier supply layer is provided.
    Type: Grant
    Filed: November 4, 2016
    Date of Patent: September 21, 2021
    Assignee: SONY CORPORATION
    Inventors: Shigeru Kanematsu, Katsuhiko Takeuchi, Masashi Yanagita, Shinichi Wada
  • Publication number: 20210150507
    Abstract: A serving system may comprise an acquiring unit configured to acquire order information from an external terminal, the order information indicating a content of an order inputted to the external terminal by a user; a presenting unit configured to present the content of the order indicated by the acquired order information to a serving entity that is to serve a serving-target article corresponding to the content; and a delivery vehicle configured to deliver the serving-target article corresponding to the presented content of the order to the user, and including a traction mechanism provided with a power source.
    Type: Application
    Filed: November 11, 2020
    Publication date: May 20, 2021
    Inventors: Makoto Kakuchi, Masashi Takahashi, Shunji Inoue, Takumi Hamajima, Hiroaki Sugiyama, Nobukatsu Fujishita, Katsuhiko Takeuchi, Tomoya Shimizu
  • Publication number: 20210111277
    Abstract: [Overview] [Problem to be Solved] To provide a switching transistor and a semiconductor module having lower distortion generated in a signal. [Solution] A switching transistor including: a channel layer including a compound semiconductor and having sheet electron density equal to or higher than 1.7×1013 cm?2; a barrier layer formed on the channel layer by using a compound semiconductor that is of a different type from the channel layer; a gate electrode provided on the barrier layer; and a source electrode and a drain electrode provided on the barrier layer with the gate electrode interposed between the source electrode and the drain electrode.
    Type: Application
    Filed: March 20, 2019
    Publication date: April 15, 2021
    Inventors: SATOSHI TANIGUCHI, MASASHI YANAGITA, KATSUHIKO TAKEUCHI, SHIGERU KANEMATSU, TAKANORI HIGASHI
  • Publication number: 20210043744
    Abstract: A semiconductor device including: a semiconductor layer; an inter-layer insulating film having a through hole and a low-dielectric constant region; a gate electrode including an embedded section and a widened section; and a gate insulating film provided between the embedded section of the gate electrode and the semiconductor layer. The through hole is provided to be opposed to the semiconductor layer. The low-dielectric constant region is provided to at least a portion of an area around the through hole. The embedded section is embedded in the through hole of the inter-layer insulating film. The widened section is opposed to the semiconductor layer with the inter-layer insulating film interposed between the widened section and the semiconductor layer and is widened to an area around the embedded section.
    Type: Application
    Filed: February 14, 2019
    Publication date: February 11, 2021
    Inventor: KATSUHIKO TAKEUCHI
  • Publication number: 20190383530
    Abstract: A heat exchanger 10 to be used in a magnetic heat pump device includes: an assembly 11 which is formed by bundling wires 12; a case 13 which accommodates the assembly 11 and is provided with at least one cutout 145 or 146; and a filling portion 16 which is filled in the cutout 145 or 146, in which the wire 12 is formed of a magnetocaloric material having a magnetocaloric effect and the filling portion 16 is in close contact with an outer periphery of the assembly 11.
    Type: Application
    Filed: December 18, 2017
    Publication date: December 19, 2019
    Applicant: Fujikura Ltd.
    Inventors: Masahiro Kondo, Kohki Ishikawa, Katsuhiko Takeuchi, Takeshi Kizaki, Ryujiro Nomura
  • Patent number: 10396081
    Abstract: A semiconductor device includes a layered body, a gate electrode, a source electrode, a drain electrode, and a cap layer. The layered body includes a channel layer and a first low resistance region. The channel layer is made of a compound semiconductor. The first low resistance region is provided in a portion on surface side of the layered body. The gate electrode, the source electrode, and the drain electrode are each provided on top surface side of the layered body. The cap layer is provided between the first low resistance region and one or both of the source electrode and the drain electrode.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: August 27, 2019
    Assignee: Sony Corporation
    Inventor: Katsuhiko Takeuchi
  • Publication number: 20190049158
    Abstract: [Object] To provide a wire capable of obtaining a wide temperature span. [Solving Means] An outer surface 121 of a wire 12A formed of a magnetocaloric material having a magnetocaloric effect partially has at least one of a concave portion 122 and a convex portion 123, the concave portion 122 is recessed in a radial direction of the wire 12A, and the convex portion 123 protrudes in the radial direction in a longitudinal direction of the wire 12A.
    Type: Application
    Filed: February 28, 2018
    Publication date: February 14, 2019
    Applicant: Fujikura Ltd.
    Inventors: Ryujiro Nomura, Takeshi Kizaki, Katsuhiko Takeuchi, Masahiro Kondo, Kohki Ishikawa
  • Patent number: 10199473
    Abstract: Provided is a semiconductor device that includes a drain electrode and a source electrode, a gate electrode, one or more gate-electrode extensions, and a link. The drain electrode and the source electrode have a planar shape of combs in mesh with each other. The gate electrode is provided between the drain electrode and the source electrode, and has a meandering planar shape. The one or more gate-electrode extensions are projected from the gate electrode. The link is confronted with one or both of the drain electrode and the source electrode, and couples the one or more gate-electrode extensions together.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: February 5, 2019
    Assignee: Sony Corporation
    Inventor: Katsuhiko Takeuchi
  • Publication number: 20190035922
    Abstract: A semiconductor device includes a substrate and a first contact layer on the substrate. The semiconductor device includes a channel layer on the first contact layer and a barrier layer on the channel layer. The semiconductor device includes a gate electrode on at least one side surface of the barrier layer and a second contact layer on the channel layer. The semiconductor device includes a first electrode on the first contact layer and a second electrode on the second contact layer.
    Type: Application
    Filed: January 13, 2017
    Publication date: January 31, 2019
    Applicant: SONY CORPORATION
    Inventors: Katsuhiko TAKEUCHI, Shigeru KANEMATSU, Masashi YANAGITA
  • Publication number: 20180358359
    Abstract: [Object] To provide a transistor, a semiconductor device, and an electronic apparatus with reduced parasitic resistance. [Solution] A transistor including: a carrier transit layer including a compound semiconductor; a carrier supply layer provided on and in contact with the carrier transit layer and including a compound semiconductor of a different type from the carrier transit layer; a gate electrode provided on the carrier supply layer; and a source electrode and a drain electrode provided on another surface of the carrier transit layer that is opposite to one surface on which the carrier supply layer is provided.
    Type: Application
    Filed: November 4, 2016
    Publication date: December 13, 2018
    Inventors: SHIGERU KANEMATSU, KATSUHIKO TAKEUCHI, MASASHI YANAGITA, SHINICHI WADA
  • Publication number: 20180350490
    Abstract: Provided is a gadolinium wire rod including gadolinium as a main component and having a Vickers hardness (HV) 120 or less.
    Type: Application
    Filed: March 1, 2018
    Publication date: December 6, 2018
    Applicant: Fujikura Ltd.
    Inventors: Ryujiro Nomura, Takeshi Kizaki, Kota Ueno, Katsuhiko Takeuchi, Masahiro Kondo, Kohki Ishikawa