Abstract: A mode set entry circuit outputs a latch timing signal at the timing at which the combination of a plurality of commands is detected. A first address latch circuit retains mode designation data for designating the operation mode in response to the latch timing signal and outputs the retained mode designation data. Next, a second address latch circuit retains the mode designation data outputted by the first address latch circuit in response to a latch timing signal indicating the end of the commands in the combination of the plural commands, and outputs the retained mode designation data.

Abstract: A process for producing an antibody composition using a cell, which comprises using a cell resistant to a lectin which recognizes a sugar chain in which 1-position of fucose is bound to 6-position of N-acetylglucosamine in the reducing end through &agr;-bond in a complex N-glycoside-linked sugar chain, and a cell used for the process.

Abstract: Operating margins of a semiconductor integrated circuit are reliably tested at low power consumption by switching power supply circuits between normal operation mode wherein a first step-up power supply serves both memory core and a step-down power supply, and testing mode wherein the memory core is powered by an external testing power supply that provides a fluctuating voltage for testing, and the step-down power supply is served by a second step-up power supply.

Abstract: A cell in which the activity of a protein relating to transport of an intracellular sugar nucleotide, GDP-fucose, to the Golgi body is more decreased or deleted than its parent cell; a process for producing an antibody composition using the cell; a transgenic non-human animal or plant or the progenies thereof, in which genome is modified so as to have a decreased or deleted activity of a protein relating to transport of an intracellular sugar nucleotide, GDP-fucose, to the Golgi body; a process for producing an antibody composition from the animal or plant; and a medicament comprising the antibody composition.

Abstract: A cell in which genome is modified so as to have a more decreased or deleted activity of an enzyme relating to modification of a sugar chain in which 1-position of fucose is bound to 6-position of N-acetylglucosamine in the reducing end through &agr;-bond in a complex N-glycoside-linked sugar chain than its parent cell, and a process for producing an antibody composition using the cell.

Abstract: The present invention provides a physiologically active peptide, a DNA encoding the peptide, an antibody which recognizes the peptide, and application methods thereof useful in screening and developing a therapeutic agent for diseases which accompany infection and inflammation, diseases which accompany abnormal differentiation and proliferation of smooth muscle cells, diseases which accompany abnormal activation of fibroblasts, diseases which accompany abnormal activation of a synovial tissue, diseases which accompany disorder of pancreatic &bgr; cells, diseases which accompany abnormality of osteoblasts or osteoclasts, diseases which accompany abnormal activation of immunocytes, diseases which accompany disorder of a blood vessel, diseases of an eye based on angiogenesis, diseases which accompany neopla, diseases in which linkage to gene regions of a major histocompatibility antigen is confirmed, and the like.

Abstract: First and second voltage generators generate a first internal power supply voltage to be supplied to a first internal power supply line and a second internal power supply voltage to be supplied to a second internal power supply line, respectively. A short circuit shorts the first and second internal power supply lines when operations of both the first and second voltage generators are suspended. The first and second internal power supply lines become floating, and charges stored in the respective internal power supply lines drain out gradually. Here, since the charges are redistributed to both of the internal power supply lines, the first and second internal power supply voltages become equal in value as they drop off. Consequently, the first and second internal power supply voltages can be prevented from inversion, and internal circuits connected to both the first and second internal power supply lines can be precluded from malfunctioning.

Abstract: A method of preparing a sulfur-containing compound having at least one thio group in the molecules by reacting a thiol compound with an organic compound having at least one functional group capable of forming a thio group in the molecules upon reacting with a mercapto group in the presence of a basic compound, wherein the number of moles of water contained in the reaction system is set to be not larger than 7.5 times as large as the number of moles obtained by multiplying the number of moles of the thiol compound to be reacted by a number of mercapto groups present in one molecule of the thiol compound.

Abstract: A redundancy memory circuit stores a defect address indicating a defective memory cell row. A redundancy control circuit disables the defective memory cell row corresponding to the defect address stored in the redundancy memory circuit and enables a redundancy memory cell row in the memory block containing the defective memory cell row. Moreover, in the other memory blocks, the redundancy control circuit disables memory cell rows corresponding to the defective memory cell row and enables redundancy memory cell rows instead of these memory cell rows. Consequently, not only the memory block having the defective memory cell row but one of the memory cell rows in the other memory blocks is always also relieved. Thus, the redundancy memory circuit can be shared among all the memory blocks with a reduction in the number of redundancy memory circuits. As a result, the semiconductor memory can be reduced in chip size.

Abstract: A memory circuit has: a real cell array; a parity generating circuit for generating a parity bit from data of the real cell array; a parity cell array; a refresh control circuit, which sequentially refreshes the real cell array, and when an internal refresh request and a read request coincide, prioritizes a refresh operation; a data recovery section, which, in accordance with the parity bit read out from the parity cell array, recovers data read out from the real cell array; and an output circuit for outputting data from the real cell array. Further, the memory circuit has a test control circuit, which, at a first test mode, prohibits a refresh operation for the real cell array to output data read out from the real cell array, and, at a second test mode, controls the output circuit so as to output data read out from the parity cell array.

Abstract: First and second voltage generators generate a first internal power supply voltage to be supplied to a first internal power supply line and a second internal power supply voltage to be supplied to a second internal power supply line, respectively. A short circuit shorts the first and second internal power supply lines when operations of both the first and second voltage generators are suspended. The first and second internal power supply lines become floating, and charges stored in the respective internal power supply lines drain out gradually. Here, since the charges are redistributed to both of the internal power supply lines, the first and second internal power supply voltages become equal in value as they drop off. Consequently, the first and second internal power supply voltages can be prevented from inversion, and internal circuits connected to both the first and second internal power supply lines can be precluded from malfunctioning.

Abstract: Operating margins of a semiconductor integrated circuit are reliably tested at low power consumption by switching power supply circuits between normal operation mode wherein a first step-up power supply serves both memory core and a step-down power supply, and testing mode wherein the memory core is powered by an external testing power supply that provides a fluctuating voltage for testing, and the step-down power supply is served by a second step-up power supply.

Abstract: A power supply circuit includes a first NMOS-type current mirror circuit which compares a first potential with a second potential, a second NMOS-type current mirror circuit which compares the first potential with a third potential, and a potential setting circuit which adjusts the first potential in response to outputs of the first and second NMOS-type current mirror circuits, such that the first potential falls between the second potential and the third potential.

Abstract: Upon receiving a level of a second node through a third switch in the first half of a first period, a holding circuit outputs it as a fuse signal indicating a blown-out state of a fuse. Since the third switch turns off in the second half of the first period, a change in level of the second node occurring thereafter will not affect data in the holding circuit, whereby prevents malfunction of a fuse circuit. With the fuse blown, a level of a first node gets fixed at that of a second power supply line after the first period. This eliminates a voltage difference between both ends of the fuse, thereby preventing a growback. No occurrence of growback makes just one fuse blowing sufficient for the fuse circuit even with the fuse not completely cut off. This consequently shortens a time for blowing the fuse in a test process.

Abstract: Upon receiving a level of a second node through a third switch in the first half of a first period, a holding circuit outputs it as a fuse signal indicating a blown-out state of a fuse. Since the third switch turns off in the second half of the first period, a change in level of the second node occurring thereafter will not affect data in the holding circuit, whereby prevents malfunction of a fuse circuit. With the fuse blown, a level of a first node gets fixed at that of a second power supply line after the first period. This eliminates a voltage difference between both ends of the fuse, thereby preventing a growback. No occurrence of growback makes just one fuse blowing sufficient for the fuse circuit even with the fuse not completely cut off. This consequently shortens a time for blowing the fuse in a test process.

Abstract: A redundancy memory circuit stores a defect address indicating a defective memory cell row. A redundancy control circuit disables the defective memory cell row corresponding to the defect address stored in the redundancy memory circuit and enables a redundancy memory cell row in the memory block containing the defective memory cell row. Moreover, in the other memory blocks, the redundancy control circuit disables memory cell rows corresponding to the defective memory cell row and enables redundancy memory cell rows instead of these memory cell rows. Consequently, not only the memory block having the defective memory cell row but one of the memory cell rows in the other memory blocks is always also relieved. Thus, the redundancy memory circuit can be shared among all the memory blocks with a reduction in the number of redundancy memory circuits. As a result, the semiconductor memory can be reduced in chip size.

Abstract: There is disclosed a polymerizable sulfur-containing (meth)acrylate, it has a high refractive index, a great Abbe's number and excellent light resistance and is suitable for the production of a transparent resin which rarely smells at the time of molding and is further excellent in storage stability. A polymerizable composition containing the (meth)acrylate and an optical lens which is a cured product of the composition are also disclosed.

Abstract: A semiconductor device includes a plurality of word lines selectable in a predetermined mode, and a circuit that precharges the plurality of word lines selected in the predetermined mode in a time division manner.

Abstract: An on-seat occupant detector apparatus includes a seat occupancy sensor made up of an optical wave guide provided in the seat for allowing the passage of light. The optical wave guide has a light transmissive portion possessing a curvature that is variable, with the optical wave guide changing the physical quantity of the light passing through the light transmissive portion when the curvature varies as a result of occupancy of the seat. The sensor also includes a light emitting device for inputting light into the optical wave guide, a light receiving device for receiving light outputted from the optical wave guide, and a detecting device which detects occupancy of the seat when the physical quantity of light passing through the light transmissive portion changes due to a change in the curvature of the transmissive portion as a result of the occupancy of the seat.

Abstract: A semiconductor device includes a plurality of word lines selectable in a predetermined mode, and a circuit that precharges the plurality of word lines selected in the predetermined mode in a time division manner.