Abstract: This invention relates to a semiconductor memory having a high speed operation and a high integration density. When a high integration semiconductor memory is applied to a large scale computer system, storage data must be erased at a high speed for data security. The present invention erases the storage data by a method which is different from the write method of conventional prior art. In the invention, the erasing operation is made by continuously selecting word lines while sense amplifiers are kept in this on-state. The present invention includes a control circuit for attaining such an operation, and can be used for a semiconductor memory implemented in a computer system accessed by a plurality of users.

Abstract: A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of intersection between the data lines and the word lines. The RAM includes a P-type semiconductor substrate and an N-type well region formed in the substrate. The memory cells are disposed within the well, and the sense amplifier, which is connected to the date lines, is constructed of a pair of N-channel MOSFETs formed in the semiconductor substrate and a pair of P-channel MOSFETs formed in the well region.

Abstract: A semiconductor memory device is provided in which an electrode applied with the power supply voltage or the ground voltage is provided on an insulating layer over the drain and/or the gate of the MOS transistors constituting the memory cell of a static memory device, thereby to increasing the capacitance of the storing node of the memory cell. This semiconductor memory device significantly reduces the occurrence of soft errors.

Abstract: Disclosed is a dynamic RAM device capable of initiating and cancelling the test mode in response to the combinations of the row address and column address strobe signals with the write enable signal, which combinations are left unused in the normal operating mode, instead of increasing the number of external control signals.

Abstract: A static random access memory cell in which capacitors are electrically connected to storage nodes, so that the memory cell will not suffer from soft error even when it is hit by alpha particles. The memory cell has MOS transistors, capacitors constituted by two polycrystalline silicon layers, and resistors constituted by a polycrystalline silicon layer, that are formed on a semiconductor substrate.

Abstract: A semiconductor memory is provided with automatic refresh means including a timer, a refresh counter and a refresh buffer each formed on a semiconductor chip mounted with an asynchronous memory, for automatically performing a periodic refresh operation on the basis of a basic clock signal which is generated in response to the detection of a logical change in the output of the refresh counter. The automatic refresh counter includes means for performing one of a read operation and a write operation which are based upon a regular address signal asynchronous with the periodic refresh operation, in preference to the periodic refresh operation.

Abstract: A semiconductor memory having an error correcting function is provided, which has a device by which the user finds no difficulty in making use of the semiconductor memory and can test it with ease. In the semiconductor memory, a signal indicative of the completion of the preparation for reading/writing is outputted from the memory so that the user, after detecting the output of this signal, performs reading/writing data. To facilitate tests, such as a memory cell test for a redundant bit (check bit), an encoding circuit test and a decoding circuit test, the present invention provides that the arranged tests can be made independently of each other.

Abstract: A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of intersection between the data lines and the word lines. The RAM includes a P-type semiconductor substrate and an N-type well region formed in the substrate. The memory cells are disposed within the well, and the sense amplifier, which is connected to the data lines, is constructed of a pair of N-channel MOSFETs formed in the semiconductor substrate and a pair of P-channel MOSFETs formed in the well region.

Abstract: In a semiconductor memory for reading and writing of stored charge in an X-Y address system by arranging a plurality of memory cells each including a capacitance element and one MOS-FET in matrix, this invention discloses a semiconductor memory using multiple level storage structure for read and write of at least more than two multi-level data stored in the capacitance elements, by applying a multi-level step voltage to the plate electrode of the capacitance or to the gate electrode of MOS-FET so as to write and read signal charge.

Abstract: A semiconductor memory device is proposed wherein at least an array comprising a plurality of memory cells each having at least one capacity, a select mechanism for specifying the position of each memory cell, data lines connected to said memory cells for transmitting the data and a data writing and a data reading mechanisms are provided.

Abstract: A semiconductor memory using a dynamic memory device, wherein a battery supplies a power source voltage and a substrate bias voltage when the memory is cut off from an external device, and a refresh control circuit changes in refresh timing of the memory device in accordance with the leakage current of the memory device. The power consumption of the memory can thus be reduced and the data can be kept for an extended period without an external power source.

Abstract: In a semiconductor memory includes a memory array consisting of a plurality of memory cells respectively having at least one storage capacitor, an addressing circuit which designates location of each memory cell, data lines which transmit data connected to said memory cells and data writing and reading circuits connected to said data lines. The semiconductor memory has a multiple level storage structure. In particular, the memory includes an arrangement for sequentially applying, on a time series basis, different voltages of at least 3 levels or more to the gate of a switching MOS transistor of said memory cells, a bias charge supplying means as said data reading circuit and a column register providing at least two or more storage cells which temporarily store said data.

Abstract: An insulated gate field effect transistor is formed in one surface of a semiconductor substrate. The surface portion of a channel has an impurity distribution of the conduction type opposite to that of the substrate, which the deeper portion of the channel has an impurity distribution of the same conduction type as that of the substrate. Moreover, at least one of a source and a drain is formed of such an impurity layer of the conduction type opposite to that of the substrate as has its impurity distribution gently sloped by double diffusion processes.

Abstract: A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of intersection between the data lines and the word lines. The RAM includes a P-type semiconductor substrate and an N-type well region formed in the substrate. The memory cells are disposed within the well, and the sense amplifier, which is connected to the date lines, is constructed of a pair of N-channel MOSFETS formed in the semiconductor substrate and a pair of P-channel MOSFETs formed in the well region.

Abstract: In a semiconductor memory in which a large number of memory cells are arrayed in the shape of a matrix, arrangements are provided for a high-sensitivity read-out. In one embodiment, a writing circuit, a voltage amplifier and a sense amplifier are successively connected to a data line that connects input and output ends of the memory cells in an identical row, with the voltage amplifier being formed as a CTD voltage amplifier that is composed of two charge transfer gates and a driving gate located between them. In accordance with another embodiment, a charge supplying circuit and a charge transfer circuit can be coupled between the memory cells and the sense amplifier to allow information transfer without any substantial loss.

Abstract: A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of intersection between the data lines and the word lines. The RAM includes a P-type semiconductor substrate and an N-type well region formed in the substrate. The memory cells are disposed within the well, and the sense amplifier, which is connected to the data lines, is constructed of a pair of N-channel MOSFETs formed in the semiconductor substrate and a pair of P-channel MOSFETs formed in the well region.

Abstract: A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of intersection between the data lines and the word lines. The RAM includes a P-type semiconductor substrate and an N-type well region formed in the substrate. The memory cells are disposed within the well, and the sense amplifier, which is connected to the data lines, is constructed of a pair of N-channel MOSFETs formed in the semiconductor substrate and a pair of P-channel MOSFETs formed in the well region.

Abstract: A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of intersection between the data lines and the word lines. The RAM includes a P-type semiconductor substrate and an N-type well region formed in the substrate. The memory cells are disposed within the well, and the sense amplifier, which is connected to the data lines, is constructed of a pair of N-channel MOSFETs formed in the semiconductor substrate and a pair of P-channel MOSFETs formed in the well region.

Abstract: A programmable semiconductor integrated circuitry including a circuit programming element is disclosed. The circuit programming element can be activated in a short-circuit mode by the irradiation of a laser or electron beam or by ion implantation so that it is converted from its original nonconductive state into a conductive or conductable state, thereby providing electrical connection between circuits and/or circuit elements of the integrated circuitry for a desired circuit programming such as circuit creation, circuit conversion or circuit substitution.

Abstract: In a dynamic monolithic memory including a plurality of memory cells each of which comprises a capacitance and a switching field-effect transistor, the source and drain electrodes of the transistor are connected to a data line and the capacitance, respectively. Upon reading a memory cell, the transistor is switched on when difference between the data line voltage and the word line voltage applied to a gate electrode of the transistor exceeds a threshold voltage of the transistor.