Abstract: A wash water processing apparatus of reusing wash water includes: a washing processing part washing a subject to be washed; a wash water accommodation part into which processed water used in a washing process in the washing processing part is once accommodated; a sterilization and purification unit causing, while acting with an ozone supply function, ozone water to be contained in the processed water flowing through the wash water accommodation part in a circular manner; and a filtration mechanism part configured to include a filter and an ion-exchange resin and sequentially filtrating the processed water to be reused as wash water in the washing processing part, as the ozone water is supplied as the processed water is mixed to dilute an ozone concentration in the wash water accommodation part. In a state where the ozone concentration is adjusted, the processed water is passed through the filter and the ion-exchange resin.

Abstract: A semiconductor device includes a first electrode, a second electrode, a third electrode located between the first electrode and the second electrode, a first semiconductor layer connected to the first electrode, a second semiconductor layer connected to the second electrode, a third semiconductor layer of a second conductivity type, and a fourth semiconductor layer of the second conductivity type. The third electrode includes first and second portions. The first semiconductor layer faces the first portion via an insulating layer. The first and second semiconductor layers are of a first conductivity type and include silicon and carbon. A carrier concentration of the fourth semiconductor layer is greater than a carrier concentration of the third semiconductor layer.

Abstract: The present technology relates to a light receiving element, a distance measuring system, and an electronic device capable of reducing unintended edge breakdown in a case where a pixel is miniaturized. A light receiving element includes a pixel that includes a PN junction region in which a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type opposite to the first conductivity type are joined, and a third semiconductor region of the first conductivity type that is not connected to any wiring outside the first semiconductor region near a first surface of a substrate on which a wiring that supplies a predetermined power supply voltage to the first semiconductor region is formed. The present technology can be applied to, for example, a distance measuring sensor that receives reflected light and measures a distance, and the like.

Abstract: According to one embodiment, a silicon carbide semiconductor device includes a first electrode, a second electrode, a first semiconductor layer, a plurality of first semiconductor pillar regions of a first conductivity type, a second semiconductor pillar region of a second conductivity type. The first semiconductor pillar regions include a first region has a first impurity concentration and second region has a second impurity concentration higher than the first impurity concentration. The second semiconductor pillar regions include a third region has a third impurity concentration and a fourth region has a fourth impurity concentration higher than the third impurity concentration.

Abstract: A semiconductor device includes a first electrode, a first semiconductor region of a first conductivity type having first and second regions, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a gate electrode, a fourth semiconductor region of the second conductivity type between the first region and the gate electrode, fifth semiconductor regions of the second conductivity type, each having a first concentration of impurities of the second conductivity type, sixth semiconductor regions of the second conductivity type, each having a second concentration of impurities of the second conductivity type that is lower than the first concentration, and a second electrode. The fifth semiconductor regions are located around the fourth semiconductor region in a first plane perpendicular to the first direction. The sixth semiconductor regions are located around the second semiconductor region in a second plane perpendicular to the first direction.

Abstract: A semiconductor device of an embodiment includes a trench in a silicon carbide layer and extending in a first direction, a gate electrode in the trench, first, second, third and fourth silicon carbide regions disposed in the silicon carbide layer in the first direction in this order, first and third silicon carbide regions having first conductive type, second and fourth silicon carbide regions having second conductive type, fifth, sixth, seventh and eighth silicon carbide regions disposed in the silicon carbide layer in the first direction in this order above the first to fourth silicon carbide regions, fifth and seventh silicon carbide regions having first conductive type higher than first and third silicon carbide regions, sixth and eighth silicon carbide regions having second conductive type higher than second and fourth silicon carbide regions, a ninth silicon carbide region of a first conductive type above the fifth to eighth silicon carbide regions.

Abstract: According to one embodiment, a semiconductor device includes first and second electrodes, first to fifth semiconductor regions, and a gate electrode. The first semiconductor region is located on the first electrode. The first semiconductor region includes a first region. The gate electrode is located on the first semiconductor region with a gate insulating layer interposed. The second semiconductor region faces the gate electrode via the gate insulating layer in a second direction perpendicular to a first direction. The third semiconductor region is located between the first and second semiconductor regions. A length in the second direction of a lower portion of the third semiconductor region is greater than a length in the second direction of an upper portion of the third semiconductor region. The fourth semiconductor region is located between the third semiconductor region and the gate electrode. The fifth semiconductor region is located on the second semiconductor region.

Abstract: A semiconductor device includes first, second and control electrodes, and a semiconductor part between the first and second electrode. The semiconductor part includes first and third layers of a first conductive type, and second, fourth and fifth layers of a second conductive type. The first layer extends between the first and second electrodes. The second layer is provided between the first layer and the second electrode. The third layer is partially provided on the second layer between the second layer and the second electrode. A first fourth layer and a second fourth layer are provided in the first layer. The fifth layer is provided between the first layer and the second layer. The fifth layer is partially provided on the first layer between the first fourth layer and the second fourth layer. The control electrode is provided between the second electrode and each of the fourth layers.

Abstract: According to one embodiment, a semiconductor device includes first and second electrodes, first to sixth semiconductor regions, a gate electrode, and a conductive part. The first semiconductor region is located on the first electrode. The first semiconductor region includes first and second regions. The second semiconductor region is located on the first region. The gate electrode is located on the second semiconductor region with a gate insulating layer interposed. The third semiconductor region is located on the first region and is separated from the second semiconductor region. The conductive part is located on the third semiconductor region with an insulating layer interposed. The fourth semiconductor region is located on the second region. The fifth semiconductor region is located on a portion of the fourth semiconductor region. The sixth semiconductor region contacts the third semiconductor region. The second electrode is located on the fourth and fifth semiconductor regions.

Abstract: A semiconductor device includes a first silicon carbide region of a first conductivity type, a second silicon carbide region of a second conductivity type on the first region, and a third silicon carbide region of a second conductivity type on the second region. Fourth and fifth silicon carbide region of the first conductivity type are on the third region. A first electrode has a first portion between the fourth region and fifth region in a first direction. A metal silicide layer is between the first portion and the third region, between the first portion and the fourth region in the first direction, and between the first portion and the fifth silicon carbide region in the first direction.

Abstract: A photodetector including: an amplification region that includes a PN junction provided in a depth direction in a semiconductor layer and that is to be electrically coupled to a cathode; a separation region that defines a pixel region including the amplification region; a hole accumulation region that is provided along a side surface of the separation region and that is to be electrically coupled to an anode; and a gate electrode provided in a region between the amplification region and the hole accumulation region and stacked over the semiconductor layer with a gate insulating film interposed therebetween.

Abstract: A semiconductor device of an embodiment includes: a first trench in a silicon carbide layer and extending in a first direction; a second trench and a third trench located in a second direction orthogonal to the first direction with respect to the first trench and adjacent to each other in the first direction, n type first silicon carbide region, p type second silicon carbide region on the first silicon carbide region, n type third silicon carbide region on the second silicon carbide region, p type fourth silicon carbide region between the first silicon carbide region and the second trench, and p type fifth silicon carbide region located between the first silicon carbide region and the third trench; a gate electrode in the first trench; a first electrode; and a second electrode. A part of the first silicon carbide region is located between the second trench and the third trench.

Abstract: A semiconductor device of an embodiment includes a first trench extending in a first direction in a silicon carbide layer; a second trench and a third trench adjacent to each other in the first direction; a first silicon carbide region of n type; a second silicon carbide region of p type on the first silicon carbide region; a third silicon carbide region of n type on the second silicon carbide region; a fourth silicon carbide region of p type between the first silicon carbide region and the second trench; a fifth silicon carbide region of p type between the first silicon carbide region and the third trench; a gate electrode in the first trench; a first electrode, part of which is in the second trench, the first electrode contacting the first silicon carbide region between the fourth silicon carbide region and the fifth silicon carbide region; and a second electrode.

Abstract: A semiconductor device of an embodiment includes: a first trench located in a silicon carbide layer extending in a first direction; a second trench and a third trench adjacent to each other in the first direction; n type first silicon carbide region; p type second silicon carbide region on the first silicon carbide region; n type third silicon carbide region on the second silicon carbide region; p type fourth silicon carbide region between the first silicon carbide region and the second trench; p type fifth silicon carbide region between the first silicon carbide region and the third trench; p type sixth silicon carbide region shallower than the second trench between the second trench and the third trench and having a p type impurity concentration higher than that of the second silicon carbide region; a gate electrode in the first trench; a first electrode, and a second electrode.

Abstract: A semiconductor device of an embodiment includes an element region and a termination region surrounding the element region. The element region includes a gate trench, a first silicon carbide region of n-type, a second silicon carbide region of p-type on the first silicon carbide region, a third silicon carbide region of n-type on the second silicon carbide region, and a fourth silicon carbide region of p-type sandwiches the first silicon carbide region and the second silicon carbide region with the gate trench, the fourth silicon carbide region being deeper than the gate trench. The termination region includes a first trench surrounding the element region, and a fifth silicon carbide region of p-type between the first trench and the first silicon carbide region, the fifth silicon carbide region same or shallower than the fourth silicon carbide region. The semiconductor device includes a gate electrode, a first electrode, and a second electrode.

Abstract: A semiconductor device of an embodiment includes a first trench extending in a first direction in a silicon carbide layer; a second trench and a third trench adjacent to each other in the first direction; a first silicon carbide region of n type; a second silicon carbide region of p type on the first silicon carbide region; a third silicon carbide region of n type on the second silicon carbide region; a fourth silicon carbide region of p type between the first silicon carbide region and the second trench; a fifth silicon carbide region of p type between the first silicon carbide region and the third trench; a gate electrode in the first trench; a first electrode, part of which is in the second trench, the first electrode contacting the first silicon carbide region between the fourth silicon carbide region and the fifth silicon carbide region; and a second electrode.

Abstract: A semiconductor device of an embodiment includes: a first trench located in a silicon carbide layer extending in a first direction; a second trench and a third trench adjacent to each other in the first direction; n type first silicon carbide region; p type second silicon carbide region on the first silicon carbide region; n type third silicon carbide region on the second silicon carbide region; p type fourth silicon carbide region between the first silicon carbide region and the second trench; p type fifth silicon carbide region between the first silicon carbide region and the third trench; p type sixth silicon carbide region shallower than the second trench between the second trench and the third trench and having a p type impurity concentration higher than that of the second silicon carbide region; a gate electrode in the first trench; a first electrode, and a second electrode.

Abstract: A semiconductor device of an embodiment includes: a first trench in a silicon carbide layer and extending in a first direction; a second trench and a third trench located in a second direction orthogonal to the first direction with respect to the first trench and adjacent to each other in the first direction, n type first silicon carbide region, p type second silicon carbide region on the first silicon carbide region, n type third silicon carbide region on the second silicon carbide region, p type fourth silicon carbide region between the first silicon carbide region and the second trench, and p type fifth silicon carbide region located between the first silicon carbide region and the third trench; a gate electrode in the first trench; a first electrode; and a second electrode. A part of the first silicon carbide region is located between the second trench and the third trench.

Abstract: A semiconductor device according to an embodiment includes: a silicon carbide layer having a first plane, a second plane facing the first plane, a first trench, a second trench, an n-type first silicon carbide region, a p-type second silicon carbide region between the first silicon carbide region and the first plane, an n-type third silicon carbide region between the second silicon carbide region and the first plane, and a p-type fourth silicon carbide region between the second trench and the first silicon carbide region; a gate electrode being located in the first trench; a gate insulating layer; a first electrode, a portion of the first electrode being located in the second trench; a second electrode; and an interlayer insulating layer being located between the gate electrode and the first electrode, in which an interface between the first electrode and the interlayer insulating layer is located in the first trench.

Abstract: A semiconductor device of an embodiment includes a SiC layer including a first trench, a second trench having first and second regions, an n-type first SiC region, a p-type second SiC region, an n-type third SiC region, a p-type fourth SiC region between the first trench and the first SiC region, and a p-type fifth SiC region between the second trench and the first SiC region and having a first portion and a second portion, a gate electrode in the first trench, a first electrode in the second trench, and a second electrode. A distance between the first trench and the first region is greater than a distance between the first trench and the second region, the first portion is separated from the fourth SiC region, the second portion contacts the fourth SiC region, the first region contacts the first portion, and the second region contacts the second portion.