Abstract: A semiconductor device includes a semiconductor substrate, an element isolating trench structure that includes an element isolating trench formed in one main surface of the semiconductor substrate, an insulating material that is formed within the element isolating trench, element formation regions that are surrounded by the element isolating trench, and semiconductor elements that are respectively formed in the element formation regions. The element isolating trench includes first element isolating trenches extending in a first direction, second element isolating trenches extending in a second direction that are at a right angle to the first direction, and third element isolating trenches extending in a third direction inclined at an angle ? (0°<?<90°) from the first direction.

Abstract: A semiconductor device includes a semiconductor substrate, an element isolating trench structure that includes an element isolating trench formed in one main surface of the semiconductor substrate, an insulating material that is formed within the element isolating trench, element formation regions that are surrounded by the element isolating trench, and semiconductor elements that are respectively formed in the element formation regions. The element isolating trench includes first element isolating trenches extending in a first direction, second element isolating trenches extending in a second direction that are at a right angle to the first direction, and third element isolating trenches extending in a third direction inclined at an angle ? (0°<?<90°) from the first direction.

Abstract: A semiconductor device includes a semiconductor substrate, an element isolating trench structure that includes an element isolating trench formed in one main surface of the semiconductor substrate, an insulating material that is formed within the element isolating trench, element formation regions that are surrounded by the element isolating trench, and semiconductor elements that are respectively formed in the element formation regions. The element isolating trench includes first element isolating trenches extending in a first direction, second element isolating trenches extending in a second direction that are at a right angle to the first direction, and third element isolating trenches extending in a third direction inclined at an angle ? (0°<?<90°) from the first direction.

Abstract: A semiconductor device includes a semiconductor substrate, an element isolating trench structure that includes an element isolating trench formed in one main surface of the semiconductor substrate, an insulating material that is formed within the element isolating trench, element formation regions that are surrounded by the element isolating trench, and semiconductor elements that are respectively formed in the element formation regions. The element isolating trench includes first element isolating trenches extending in a first direction, second element isolating trenches extending in a second direction that are at a right angle to the first direction, and third element isolating trenches extending in a third direction inclined at an angle ? (0°<?<90°) from the first direction.

Abstract: A semiconductor device includes a semiconductor substrate, an element isolating trench structure that includes an element isolating trench formed in one main surface of the semiconductor substrate, an insulating material that is formed within the element isolating trench, element formation regions that are surrounded by the element isolating trench, and semiconductor elements that are respectively formed in the element formation regions. The element isolating trench includes first element isolating trenches extending in a first direction, second element isolating trenches extending in a second direction that are at a right angle to the first direction, and third element isolating trenches extending in a third direction inclined at an angle ? (0°<?<90°) from the first direction.

Abstract: Disclosed is a semiconductor device including: a semiconductor substrate; first and second element isolating trenches that are formed in one main surface of the semiconductor substrate separately from each other; a first insulating material that is formed within the first element isolating trench; a plurality of first element formation regions that are surrounded by the first element isolating trench; first semiconductor elements that are respectively formed in the first element formation regions; a second insulating material that is formed within the second element isolating trench; a second element formation region that is surrounded by the second element isolating trench; a second semiconductor element that is formed in the second element formation region; and a stress relaxation structure that is formed between the first element isolating trench and the second element isolating trench.

Abstract: Disclosed is a semiconductor device including: a semiconductor substrate, an element isolating trench structure that includes an element isolating trench formed in one main surface of the semiconductor substrate, an insulating material that is formed within the element isolating trench, element formation regions that are surrounded by the element isolating trench, and semiconductor elements that are respectively formed in the element formation regions. The element isolating trench includes first element isolating trenches extending in a first direction, second element isolating trenches extending in a second direction that are at a right angle to the first direction, and third element isolating trenches extending in a third direction inclined at an angle ? (0°<?<90°) from the first direction.

Abstract: Disclosed is a semiconductor device including: a semiconductor substrate; first and second element isolating trenches that are formed in one main surface of the semiconductor substrate separately from each other; a first insulating material that is formed within the first element isolating trench; a plurality of first element formation regions that are surrounded by the first element isolating trench; first semiconductor elements that are respectively formed in the first element formation regions; a second insulating material that is formed within the second element isolating trench; a second element formation region that is surrounded by the second element isolating trench; a second semiconductor element that is formed in the second element formation region; and a stress relaxation structure that is formed between the first element isolating trench and the second element isolating trench.

Abstract: A semiconductor structure includes (a) a semiconductor substrate having a channel region and a first integrated impurity diffusion region including a first electric field reduction region that is formed adjacent to the channel region and which includes a plurality of specific regions separated from each other, (b) a first insulating film formed on the semiconductor substrate, and (c) a first electrode structure having a first region formed above the channel region and a second region that is formed adjacent to the first region and above the first electric field reduction region to be self-aligned with the first electric field reduction region, the semiconductor structure including one or more openings formed above the plurality of specific regions and a first opening surrounding portion surrounding the one or more openings.

Abstract: A concentric polygonal metal-oxide-semiconductor field-effect transistor is designed to avoid overlap between corners of the central drain diffusion and inner corners of the surrounding annular gate electrode. For example, the gate electrode may be reduced to separate straight segments by eliminating the corner portions. Alternatively, the drain diffusion may have a cross shape, and the outer annular source diffusion may be reduced to straight segments facing the ends of the cross, or the source and drain diffusions and gate electrodes may all be reduced to separate straight segments. By avoiding electric field concentration in the corner regions, these designs provide enhanced protection from electrostatic discharge.

Abstract: A semiconductor structure includes (a) a semiconductor substrate having a channel region and a first integrated impurity diffusion region including a first electric field reduction region that is formed adjacent to the channel region and which includes a plurality of specific regions separated from each other, (b) a first insulating film formed on the semiconductor substrate, and (c) a first electrode structure having a first region formed above the channel region and a second region that is formed adjacent to the first region and above the first electric field reduction region to be self-aligned with the first electric field reduction region, the semiconductor structure including one or more openings formed above the plurality of specific regions and a first opening surrounding portion surrounding the one or more openings.

Abstract: A method of manufacturing a semiconductor device, including forming a gate insulating film on a P type semiconductor layer, forming on the gate insulating film a gate electrode having slits at, at least an end thereof on the drain electrode forming predeterminate side, selectively implanting an N type impurity into the P type semiconductor layer with the gate electrode as a mask, effecting heat treatment to activate the impurity and integrating impurity regions in which the impurity is implanted in the slits and portions outside the gate electrode, by transverse direction thereby to form a pair of N type low-density diffused layers that overlap, at least, on the drain electrode side of the gate electrode, and forming a pair of N type high-density diffused layers spaced away from the gate electrode.

Abstract: The present invention provides a method of manufacturing a semiconductor device, comprising the steps of forming a gate insulating film (102) on a P type semiconductor layer (101), forming on the gate insulating film (102) a gate electrode (103) having slits (104) at, at least one ends thereof on the drain electrode forming predeterminate side, selectively implanting an N type impurity into the P type semiconductor layer (101) with the gate electrode (103) as a mask, effecting heat treatment to activate the impurity and integrating impurity regions in which the impurity is implanted in the slits and portions outside the gate electrode, by transverse direction thereby to form a pair of N type low-density diffused layers (107) that overlap on, at least, on the drain electrode side of the gate electrode, and forming a pair of N type high-density diffused layers (108) with being spaced away from the gate electrode (103).

Abstract: A concentric polygonal metal-oxide-semiconductor field-effect transistor is designed to avoid overlap between corners of the central drain diffusion and inner corners of the surrounding annular gate electrode. For example, the gate electrode may be reduced to separate straight segments by eliminating the corner portions. Alternatively, the drain diffusion may have a cross shape, and the outer annular source diffusion may be reduced to straight segments facing the ends of the cross, or the source and drain diffusions and gate electrodes may all be reduced to separate straight segments. By avoiding electric field concentration in the corner regions, these designs provide enhanced protection from electrostatic discharge.

Abstract: In a method of fabricating an LDMOS semiconductor device, a combined layer including a gate oxide film and a first nitride film is formed on a substrate within a first region. A mask body is formed on the combined layer within a second region that is inside of the first region. Then, first impurities are introduced into the substrate outside of the second region using the mask body as a mask. Next, second impurities are introduced into the substrate outside of the first region using the mask body and the combined layer as a mask. Finally, the introduced first and second impurities are diffused by a heat treatment so as to form a source/drain region and a well region.

Abstract: A concentric polygonal metal-oxide-semiconductor field-effect transistor is designed to avoid overlap between corners of the central drain diffusion and inner corners of the surrounding annular gate electrode. For example, the gate electrode may be reduced to separate straight segments by eliminating the corner portions. Alternatively, the drain diffusion may have a cross shape, and the outer annular source diffusion may be reduced to straight segments facing the ends of the cross, or the source and drain diffusions and gate electrodes may all be reduced to separate straight segments. By avoiding electric field concentration in the corner regions, these designs provide enhanced protection from electrostatic discharge.

Abstract: A concentric polygonal metal-oxide-semiconductor field-effect transistor is designed to avoid overlap between corners of the central drain diffusion and inner corners of the surrounding annular gate electrode. For example, the gate electrode may be reduced to separate straight segments by eliminating the corner portions. Alternatively, the drain diffusion may have a cross shape, and the outer annular source diffusion may be reduced to straight segments facing the ends of the cross, or the source and drain diffusions and gate electrodes may all be reduced to separate straight segments. By avoiding electric field concentration in the corner regions, these designs provide enhanced protection from electrostatic discharge.

Abstract: A method of manufacturing an LDMOS transistor includes providing a semiconductor substrate of a first conductivity type having a well region of a second conductivity type formed on a surface of the substrate. Ions of the first conductivity type are implanted into a part of the well region with a predetermined energy. The substrate is subjected to a heat treatment so that the implanted ions are diffused to form a diffusion region of the first conductivity type on the surface of the substrate. Then, a gate oxide layer and a gate electrode are formed on the surface of the substrate. Finally, a drain region is formed on the surface of the substrate. The predetermined energy for the implantation is set so that an accelerated oxidation during a formation of the gate oxide layer is inhibited.

Abstract: In a method of fabricating an LDMOS semiconductor device, a combined layer including a gate oxide film and a first nitride film is formed on a substrate within a first region. A mask body is formed on the combined layer within a second region that is inside of the first region. Then, first impurities are introduced into the substrate outside of the second region using the mask body as a mask. Next, second impurities are introduced into the substrate outside of the first region using the mask body and the combined layer as a mask. Finally, the introduced first and second impurities are diffused by a heat treatment so as to form a source/drain region and a well region.

Abstract: A method of manufacturing an LDMOS transistor comprises providing a semiconductor substrate of a first conductivity type having a well region of a second conductivity type formed on a surface of the substrate. Ions of the first conductivity type are implanted into a part of the well region with a predetermined energy. The substrate is subjected to a heat treatment so that the implanted ions are diffused to form a diffusion region of the first conductivity type on the surface of the substrate. Then, a gate oxide layer and a gate electrode are formed on the surface of the substrate. Finally, a drain region is formed on the surface of the substrate. The predetermined energy for the implantation is set so that an accelerated oxidation during a formation of the gate oxide layer is inhibited.