Abstract: A memory cell power supply circuit for each column includes a first PMOS transistor and a second PMOS transistor connected together in series between a first power supply and a second power supply. A connection point between the first and second PMOS transistors is output as a memory cell power supply. A control signal which is based on a column select signal and a write control signal is input to a gate terminal of the first PMOS transistor. A signal which is an inverted version of the signal input to the gate terminal of the first PMOS transistor is input to a gate terminal of the second PMOS transistor.

Abstract: A memory cell power supply circuit for each column includes a first PMOS transistor and a second PMOS transistor connected together in series between a first power supply and a second power supply. A connection point between the first and second PMOS transistors is output as a memory cell power supply. A control signal which is based on a column select signal and a write control signal is input to a gate terminal of the first PMOS transistor. A signal which is an inverted version of the signal input to the gate terminal of the first PMOS transistor is input to a gate terminal of the second PMOS transistor.

Abstract: A control circuit supplies a word line drive voltage to one of m word lines which corresponds to a memory cell to which data is to be written, during a word line drive period including a first period and a second period following the first period, to decrease current capabilities of first and second load transistors included in the memory cell during the first period, and increase the current capabilities of the first and second load transistors during the second period.

Abstract: A control circuit supplies a word line drive voltage to one of m word lines which corresponds to a memory cell to which data is to be written, during a word line drive period including a first period and a second period following the first period, to decrease current capabilities of first and second load transistors included in the memory cell during the first period, and increase the current capabilities of the first and second load transistors during the second period.

Abstract: In a semiconductor memory device 100, a non-volatile element section 4 stores information necessary for rescuing a main memory cell, as storage information, in a non-volatile element. When rescue information S3 is newly outputted by a redundancy rescue section, a rescue determination section 5 determines whether or not a main memory cell is to be rescued, based on storage information S4 stored in the non-volatile element section 4, and the rescue information S3 which is newly outputted. The non-volatile element section 4 renews the storage information based on a determination result from the rescue determination section 5. Thus, on the assumption that power is turned off each time a voltage condition is changed, the semiconductor memory device 100 is capable of determining whether or not the rescue is to be performed, based on results of testings performed under a plurality of voltage conditions.

Abstract: A semiconductor memory device is provided which can reliably detect a memory cell which has an unstable operation due to a small memory cell current. A bit line drive circuit is provided with respect to each pair of first and second bit lines, and has a configuration which can decrease a potential of a selected one of the pair of first and second bit lines. During a test operation, the first bit line in conduction with an H-side memory holding node of a memory cell is grounded for a predetermined time, thereby reducing a potential difference between the pair of first and second bit lines.

Abstract: In a semiconductor memory device 100, a non-volatile element section 4 stores information necessary for rescuing a main memory cell, as storage information, in a non-volatile element. When rescue information S3 is newly outputted by a redundancy rescue section, a rescue determination section 5 determines whether or not a main memory cell is to be rescued, based on storage information S4 stored in the non-volatile element section 4, and the rescue information S3 which is newly outputted. The non-volatile element section 4 renews the storage information based on a determination result from the rescue determination section 5. Thus, on the assumption that power is turned off each time a voltage condition is changed, the semiconductor memory device 100 is capable of determining whether or not the rescue is to be performed, based on results of testings performed under a plurality of voltage conditions.

Abstract: In data read, a single read global bit line is shared with a plurality of local bit lines.

Abstract: In data read, a single read global bit line is shared with a plurality of local bit lines.

Abstract: A static random access memory (SRAM) includes a memory array, a sense amplifier circuit, a replica circuit and a dummy cell. The replica circuit has the same elements as memory cells, and includes plural replica cells which output a signal whose level corresponds to the number of stages provided to a common replica bit line. The dummy cell is connected as a load with the common replica bit line. The source of a drive transistor of the dummy cell is connected with a power source which is at the High level. This suppresses a leak current flowing from a replica bit line to the dummy cell.

Abstract: Over a memory cell array region of a static RAM (random access memory), dummy wire patterns are formed such that each dummy wire pattern covers 2×2 horizontally and vertically-adjacent intersection points of word lines and bit lines, and horizontally-running wire channels and vertically-running wire channels are formed between the dummy wire patterns in a lattice configuration. Then, a signal line is automatically arranged to extend through any of the wire channels. The dummy wire patterns are provided in a layer lying on the word lines, and the signal line is provided as a metal line extending in the same layer as that of the dummy wire patterns.

Abstract: A semiconductor memory device is provided which can reliably detect a memory cell which has an unstable operation due to a small memory cell current. A bit line drive circuit is provided with respect to each pair of first and second bit lines, and has a configuration which can decrease a potential of a selected one of the pair of first and second bit lines. During a test operation, the first bit line in conduction with an H-side memory holding node of a memory cell is grounded for a predetermined time, thereby reducing a potential difference between the pair of first and second bit lines.

Abstract: A dummy cell includes two series-connected OFF-state transistors, one end of the series circuit which is formed by these two transistors is connected with a constant voltage source, and the other end of the series circuit is connected with a replica bit line. This suppresses a leak current flowing from the replica bit line to the dummy cell and therefore gives optimal start-up timing to a sense amplifier circuit.

Abstract: A semiconductor memory device may include: (1) a word line drive circuit, having a drive transistor disposed between a positive power supply and a word line, (2) a circuit for turning the drive transistor OFF after an output of the word line drive circuit reaches a high level, and (3) a word-line-voltage increasing circuit for increasing a voltage of the word line after the drive transistor turns OFF. The word-line-voltage increasing circuit includes a coupling capacitor, one end of which is connected to the word line, and a capacitor drive circuit, an output end of which is connected to the other end of the coupling capacitor. The capacitor drive circuit switches its output from a low level to a high level at a timing when the drive transistor is OFF.

Abstract: A memory array, a sense amplifier circuit, a replica circuit and a dummy cell are disposed. The replica circuit has the same elements as memory cells, and includes plural replica cells which output a signal whose level corresponds to the number of stages provided to a common replica bit line. The dummy cell is connected as a load with the common replica bit line. The source of a drive transistor of the dummy cell is connected with a power source which is at the High level. This suppresses a leak current flowing from a replica bit line to the dummy cell.

Abstract: Over a memory cell array region of a static RAM (random access memory), dummy wire patterns are formed such that each dummy wire pattern covers 2×2 horizontally and vertically-adjacent intersection points of word lines and bit lines, and horizontally-running wire channels and vertically-running wire channels are formed between the dummy wire patterns in a lattice configuration. Then, a signal line is automatically arranged to extend through any of the wire channels. The dummy wire patterns are provided in a layer lying on the word lines, and the signal line is provided as a metal line extending in the same layer as that of the dummy wire patterns.

Abstract: A dummy cell includes two series-connected OFF-state transistors, one end of the series circuit which is formed by these two transistors is connected with a constant voltage source, and the other end of the series circuit is connected with a replica bit line. This suppresses a leak current flowing from the replica bit line to the dummy cell and therefore gives optimal start-up timing to a sense amplifier circuit.

Abstract: Positive/negative bit lines are arranged on a second-layer interconnection the VDD power supply interconnection is arranged between the positive/negative bit lines, the word line is arranged on a third-layer interconnection, and the VSS power supply interconnection is arranged on a fourth-layer interconnection. Alternatively, the word line is arranged on the second-layer interconnection, the positive/negative bit lines are arranged on the third-layer interconnection, the VDD power supply interconnection is arranged between the positive/negative bit lines, and the VSS power supply interconnection is arranged on the fourth-layer interconnection. Alternatively, the VDD power supply interconnection is arranged on the second-layer interconnection, the positive/negative bit lines are arranged on the third-layer interconnection, the word line is arranged on the fourth-layer interconnection, and the VSS power supply interconnection is arranged on the fifth-layer interconnection.

Abstract: Positive/negative bit lines are arranged on a second-layer interconnection the VDD power supply interconnection is arranged between the positive/negative bit lines, the word line is arranged on a third-layer interconnection, and the VSS power supply interconnection is arranged on a fourth-layer interconnection. Alternatively, the word line is arranged on the second-layer interconnection, the positive/negative bit lines are arranged on the third-layer interconnection, the VDD power supply interconnection is arranged between the positive/negative bit lines, and the VSS power supply interconnection is arranged on the fourth-layer interconnection. Alternatively, the VDD power supply interconnection is arranged on the second-layer interconnection, the positive/negative bit lines are arranged on the third-layer interconnection, the word line is arranged on the fourth-layer interconnection, and the VSS power supply interconnection is arranged on the fifth-layer interconnection.

Abstract: A semiconductor memory device comprises a word line drive circuit including a drive transistor, which drives a word line; a circuit for turning the drive transistor OFF right after an output of the word line drive circuit reaches a high level; and a word-line-voltage increasing circuit for increasing a voltage of the word line after the drive transistor turns OFF. The word-line-voltage increasing circuit includes a coupling capacitor one end of which is connected to the word line, and a capacitor drive circuit an output end of which is connected to the other end of the coupling capacitor. The capacitor drive circuit switches its output from a low level to a high level at turn-OFF timing of the drive transistor. The coupling capacitor includes a wiring line running along the word line.