Abstract: A semiconductor memory device has a SRAM memory cell comprising: a first inverter including a first nMOS transistor and a first pMOS transistor; a second inverter including a second nMOS transistor and a second pMOS transistor; a third nMOS transistor; and a fourth nMOS transistor, wherein a first diffusion region forming the first and third nMOS transistors and a second diffusion region forming the second and fourth nMOS transistors, respectively, are arranged in linear shapes without having any bent part, and driving capabilities of the first and second nMOS transistors are higher than those of the third and fourth nMOS transistors.

Abstract: N-channel MOS transistors are connected to bit lines so as to correspond to the data to be read out. A constant current outputting circuit uses an off leakage current of load transistors similar to the N-channel MOS transistors as a reference current to constitute a current mirror circuit having a mirror ratio according to the number of the N-channel MOS transistors connected to each bit line. P-channel MOS transistors of the constant current outputting circuit are connected to the bit lines and supply a current according to the off leakage currents of the N-channel MOS transistors. Thus, malfunctions caused by such as off leakage currents of transistors or the like can be reliably prevented without causing an increase in access time.

Abstract: A power supply circuit according to the present invention is a power supply circuit formed on a semiconductor chip, including: an output transistor section outputting a power supply voltage; and a control circuit for controlling the output transistor section. The output transistor section is arranged in the vicinity of an external input/output terminal of the semiconductor chip.

Abstract: A semiconductor memory device has a SRAM memory cell comprising: a first inverter including a first nMOS transistor and a first pMOS transistor; a second inverter including a second nMOS transistor and a second pMOS transistor; a third nMOS transistor; and a fourth nMOS transistor, wherein a first diffusion region forming the first and third nMOS transistors and a second diffusion region forming the second and fourth nMOS transistors, respectively, are arranged in linear shapes without having any bent part, and driving capabilities of the first and second nMOS transistors are higher than those of the third and fourth nMOS transistors.

Abstract: N-channel MOS transistors are connected to bit lines so as to correspond to the data to be read out. A constant current outputting circuit uses an off leakage current of load transistors similar to the N-channel MOS transistors as a reference current to constitute a current mirror circuit having a mirror ratio according to the number of the N-channel MOS transistors connected to each bit line. P-channel MOS transistors of the constant current outputting circuit are connected to the bit lines and supply a current according to the off leakage currents of the N-channel MOS transistors. Thus, malfunctions caused by such as off leakage currents of transistors or the like can be reliably prevented without causing an increase in access time.

Abstract: A power supply circuit according to the present invention is a power supply circuit formed on a semiconductor chip, including: an output transistor section outputting a power supply voltage; and a control circuit for controlling the output transistor section. The output transistor section is arranged in the vicinity of an external input/output terminal of the semiconductor chip.

Abstract: In a switching regulator, switching noise is reduced with keeping high conversion efficiency. The switching regulator includes plural output switching transistors 21 through 23 having different on-resistances, which are operated nadescending order of on-resistance in the on operation and are operated in an ascending order of on-resistance in the off operation. In this manner, abrupt current change can be suppressed in the switching operation, resulting in reducing di/dt noise derived from a parasitic inductor 102.

Abstract: In a switching regulator, switching noise is reduced with keeping high conversion efficiency. The switching regulator includes plural output switching transistors 21 through 23 having different on-resistances, which are operated in a descending order of on-resistance in the on operation and are operated in an ascending order of on-resistance in the off operation. In this manner, abrupt current change can be suppressed in the switching operation, resulting in reducing di/dt noise derived from a parasitic inductor 102.

Abstract: A power supply circuit according to the present invention is a power supply circuit formed on a semiconductor chip, including: an output transistor section outputting a power supply voltage; and a control circuit for controlling the output transistor section. The output transistor section is arranged in the vicinity of an external input/output terminal of the semiconductor chip.

Abstract: In a level shift circuit, when a signal at a low voltage signal level applied at the signal input terminal changes from a LOW to a HIGH level, an inverter is boosted in input voltage level by a voltage booster on the basis of the voltage of a capacitor element charged through a diode element and on the basis of the input signal variation such that the inverter assumes an input voltage level above the aforesaid low voltage signal level. This enables the inverter to perform an inversion operation without fail and the signal output terminal provides a HIGH level signal at a high voltage. In addition, when the input signal changes from HIGH to LOW, an input of the inverter is pulled down directly by an N-channel transistor coupled to a ground power source to LOW. Accordingly, also in this case, the inverter performs an inversion operation without fail.

Abstract: The switching regulator of a synchronous rectifying mode comprises the first and second switches SW1, SW2 arranged in series between the power source Vdd and the ground Vss, the switch control unit 1 which controls the on-off operation of the switches SW1, SW2, and the smoothing circuit 4 which smoothes the output node potential Vnd. When the signal Sc1 indicates that the output node potential Vnd goes below the first reference potential Vr1 which is the reference to detect the occurrence of the inrush current while the first switch SW1 is in the ON state, the control circuit 10 turns off the first switch SW1. Thus, the detection of the inrush current is conducted by making use of a voltage drop due to the on resistance of the first switch SW1, so that it is unnecessary to provide a resistance element for detecting the inrush current.

Abstract: In a level shift circuit, when a signal at a low voltage signal level applied at the signal input terminal changes from a LOW to a HIGH level, an inverter is boosted in input voltage level by a voltage booster on the basis of the voltage of a capacitor element charged through a diode element and on the basis of the input signal variation such that the inverter assumes an input voltage level above the aforesaid low voltage signal level. This enables the inverter to perform an inversion operation without fail and the signal output terminal provides a HIGH level signal at a high voltage. In addition, when the input signal changes from HIGH to LOW, an input of the inverter is pulled down directly by an N-channel transistor coupled to a ground power source to LOW. Accordingly, also in this case, the inverter performs an inversion operation without fail.

Abstract: In a level shift circuit, when a signal at a low voltage signal level applied at the signal input terminal changes from a LOW to a HIGH level, an inverter is boosted in input voltage level by a voltage booster on the basis of the voltage of a capacitor element charged through a diode element and on the basis of the input signal variation such that the inverter assumes an input voltage level above the aforesaid low voltage signal level. This enables the inverter to perform an inversion operation without fail and the signal output terminal provides a HIGH level signal at a high voltage. In addition, when the input signal changes from HIGH to LOW, an input of the inverter is pulled down directly by an N-channel transistor coupled to a ground power source to LOW. Accordingly, also in this case, the inverter performs an inversion operation without fail.

Abstract: The input circuit of the present invention includes an NMOSFET. One terminal of the NMOSFET is connected to an input terminal and the gate of the NMOSFET is connected to a power supply terminal via a clamping circuit. A signal, received at the one terminal of the NMOSFET with an amplitude equal to or larger than that of a power supply voltage, is output through the other terminal of the NMOSFET with an amplitude equal to that of the power supply voltage. The input circuit further includes: a gate controller, which is connected to the other terminal of the NMOSFET; and a PMOSFET. One terminal of the PMOSFET is directly connected to the other terminal of the NMOSFET and the gate of the PMOSFET is also connected to the other terminal of the NMOSFET via the gate controller. If the voltage at the other terminal of the NMOSFET is at a high level, the gate controller turns the PMOSFET ON. Alternatively, if the voltage at the other terminal of the NMOSFET is at a low level, the gate controller turns the PMOSFET OFF.

Abstract: A power circuit including means for preventing the generation of an inrush current during the power circuit's initial operation without increasing the size of the power circuit is described. The power circuit comprises an output transistor for supplying a current from a power supply to an output terminal, and a differential amplifier for controlling the current supplied by the output transistor in such a manner as to regulate a voltage at the output terminal based on a preset reference voltage. A limiting transistor is provided as a source follower on a current path at the output stage of the differential amplifier. The gate potential of the output transistor is controlled using the source potential of the limiting transistor. Before the power circuit starts to operate, an operation controller charges a capacitor to control the gate potential of the limiting transistor so that during the initial operation of the power circuit, the capacitor is discharged by using a current source.