Patents by Inventor Katsumi Eikyu
Katsumi Eikyu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20040174756Abstract: A plurality of word lines (WL1) are provided in parallel to one another and a plurality of bit lines (BL1) are provided in parallel to one another, intersecting the word lines (WL1) thereabove. MRAM cells (MC2) are formed at intersections of the word lines and the bit lines therebetween. MRAM cells (MC3) are provided so that an easy axis indicated by the arrow has an angle of 45 degrees with respect to the bit lines and the word lines. Thus, an MRAM capable of cutting the power consumption in writing is achieved and further an MRAM capable of reducing the time required for erasing and writing operations is achieved.Type: ApplicationFiled: March 11, 2004Publication date: September 9, 2004Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Tatsuya Kunikiyo, Katsumi Eikyu, Shigenobu Maeda
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Patent number: 6741495Abstract: A plurality of word lines (WL1) are provided in parallel to one another and a plurality of bit lines (BL1) are provided in parallel to one another, intersecting the word lines (WL1) thereabove. MRAM cells (MC2) are formed at intersections of the word lines and the bit lines therebetween. MRAM cells (MC3) are provided so that an easy axis indicated by the arrow has an angle of 45 degrees with respect to the bit lines and the word lines. Thus, an MRAM capable of cutting the power consumption in writing is achieved and further an MRAM capable of reducing the time required for erasing and writing operations is achieved.Type: GrantFiled: April 28, 2003Date of Patent: May 25, 2004Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Tatsuya Kunikiyo, Katsumi Eikyu, Shigenobu Maeda
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Publication number: 20030220770Abstract: On the basis of layout information and process information, a three-dimensional TCAD conducts simulations of a three-dimensional structure while taking adversely-affecting device phenomena into account and outputs electric characteristic data corresponding to design rules defined in the layout information for the same number of times as the number of plural pieces of design rule information. A simulation result accumulating portion accumulates the electric characteristic data obtained from the three-dimensional TCAD and provides the accumulated electric characteristic data that are associated with the plural pieces of design rule information. Then, on the basis of the accumulated electric characteristic data, a design rule determining portion determines from among the plural pieces of design rule information the optimum design rule information that satisfies a reference value and outputs it as determined design rule information.Type: ApplicationFiled: October 16, 2002Publication date: November 27, 2003Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventor: Katsumi Eikyu
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Publication number: 20030218473Abstract: A CBCM measurement device includes a PMIS transistor, an NMIS transistor, a first reference conductor section connected to a first node, a second reference conductor section, with a dummy capacitor being formed between the first and second reference conductor sections, a first test conductor section connected to a second node, and a second test conductor section, with a test capacitor being formed between the first and second test conductor sections. The transistors are turned ON/OFF by using control voltages V1 and V2, and the capacitance of a target capacitor in the test capacitor is measured based on currents flowing through the first and second nodes. The capacitance measurement precision is improved by, for example, increasing a dummy capacitance.Type: ApplicationFiled: January 31, 2003Publication date: November 27, 2003Applicants: Matsushita Electric Industrial Co., Ltd., Mitsubishi Denki Kabushiki KaishaInventors: Kyoji Yamashita, Hiroyuki Umimoto, Mutsumi Kobayashi, Katsuhiro Ohtani, Tatsuya Kunikiyo, Katsumi Eikyu
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Publication number: 20030210591Abstract: A plurality of word lines (WL1) are provided in parallel to one another and a plurality of bit lines (BL1) are provided in parallel to one another, intersecting the word lines (WL1) thereabove. MRAM cells (MC2) are formed at intersections of the word lines and the bit lines therebetween. MRAM cells (MC3) are provided so that an easy axis indicated by the arrow has an angle of 45 degrees with respect to the bit lines and the word lines. Thus, an MRAM capable of cutting the power consumption in writing is achieved and further an MRAM capable of reducing the time required for erasing and writing operations is achieved.Type: ApplicationFiled: April 28, 2003Publication date: November 13, 2003Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Tatsuya Kunikiyo, Katsumi Eikyu, Shigenobu Maeda
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Publication number: 20030117151Abstract: It is an object to obtain a semiconductor device having a circuit for CBCM (Charge Based Capacitance Measurement) which can measure a capacitance value with high precision. An MOS transistor constituting a circuit for CBCM has the following structure. More specifically, source-drain regions (4) and (4′) are selectively formed in a surface of a body region (16), and extension regions (5) and (5′) are extended from tip portions of the source-drain regions (4) and (4′) opposed to each other, respectively. A gate insulating film 7 is formed between the source-drain regions (4) and (4′) including the extension regions (5) and (5′) and a gate electrode (8) is formed on the gate insulating film (7). A region corresponding to a pocket region 6 (6′) in a conventional structure having a higher impurity concentration than that of a channel region is not formed in a tip portion of the extension region 5 (5′) and a peripheral portion of the extension region (5).Type: ApplicationFiled: September 3, 2002Publication date: June 26, 2003Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Tatsuya Kunikiyo, Katsumi Eikyu, Kyoji Yamashita, Katsuhiro Ohtani, Hiroyuki Umimoto, Mutsumi Kobayashi
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Patent number: 6576965Abstract: Arsenic is ion-implanted through a thin insulative through film formed on an active region in the vicinity of a gate insulating film towards the inside of a semiconductor substrate at a dose of 3E13 cm−2 at an energy of 100 keV at a tilt angle, which is made by an ion implantation direction and a normal direction (NL), of 45 degrees with respect to a (100) surface of the semiconductor substrate, with which a channeling phenomenon can be caused. Next, phosphorus is ion-implanted towards the inside of the semiconductor substrate at a dose of 1E13 cm−2 at an energy of 50 keV at an angle with which no channeling phenomenon can be caused. After that, a sidewall is formed and then arsenic is ion-implanted towards the inside of the semiconductor substrate at a dose of 4E15 cm−2 at an energy of 50 keV at an angle with which no channeling phenomenon can be caused, to form n+ layers.Type: GrantFiled: October 8, 1999Date of Patent: June 10, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Katsumi Eikyu, Yukio Nishida
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Patent number: 6567299Abstract: A plurality of word lines (WL1) are provided in parallel to one another and a plurality of bit lines (BL1) are provided in parallel to one another, intersecting the word lines (WL1) thereabove. MRAM cells (MC2) are formed at intersections of the word lines and the bit lines therebetween. MRAM cells (MC3) are provided so that an easy axis indicated by the arrow has an angle of 45 degrees with respect to the bit lines and the word lines. Thus, an MRAM capable of cutting the power consumption in writing is achieved and further an MRAM capable of reducing the time required for erasing and writing operations is achieved.Type: GrantFiled: November 21, 2001Date of Patent: May 20, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Tatsuya Kunikiyo, Katsumi Eikyu, Shigenobu Maeda
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Publication number: 20020145902Abstract: A plurality of word lines (WL1) are provided in parallel to one another and a plurality of bit lines (BL1) are provided in parallel to one another, intersecting the word lines (WL1) thereabove. MRAM cells (MC2) are formed at intersections of the word lines and the bit lines therebetween. MRAM cells (MC3) are provided so that an easy axis indicated by the arrow has an angle of 45 degrees with respect to the bit lines and the word lines. Thus, an MRAM capable of cutting the power consumption in writing is achieved and further an MRAM capable of reducing the time required for erasing and writing operations is achieved.Type: ApplicationFiled: November 21, 2001Publication date: October 10, 2002Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Tatsuya Kunikiyo, Katsumi Eikyu, Shigenobu Maeda
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Patent number: 6461946Abstract: Both P type and N type impurities are implanted from a plurality of directions. The tilt angle &thgr; of the implantation direction against the normal of the main surface of a semiconductor substrate is fixed to 10°, and the deflection angle &phgr; is set to such four directions (X, X+90°, X+180°, and X+270°, where X is an arbitrary angle) that projecting components of a vector indicating the implantation direction are opposed to each other on two lines that cross each other at right angles along the main surface of the semiconductor substrate. Thereby, the dependency of the breakdown voltage of element isolation on the direction of a well boundary is suppressed to realize a high breakdown voltage of element isolation in all directions.Type: GrantFiled: April 30, 2001Date of Patent: October 8, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Takeshi Kitani, Katsumi Eikyu, Masao Sugiyama
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Publication number: 20020105066Abstract: Arsenic is ion-implanted through a thin insulative through film formed on an active region in the vicinity of a gate insulating film towards the inside of a semiconductor substrate at a dose of 3E13 cm−2 at an energy of 100 keV at a tilt angle, which is made by an ion implantation direction and a normal direction (NL), of 45 degrees with respect to a (100) surface of the semiconductor substrate, with which a channeling phenomenon can be caused. Next, phosphorus is ion-implanted towards the inside of the semiconductor substrate at a dose of 1E13 cm−2 at an energy of 50 keV at an angle with which no channeling phenomenon can be caused. After that, a sidewall is formed and then arsenic is ion-implanted towards the inside of the semiconductor substrate at a dose of 4E15 cm−2 at an energy of 50 keV at an angle with which no channeling phenomenon can be caused, to form n+ layers.Type: ApplicationFiled: October 8, 1999Publication date: August 8, 2002Inventors: KATSUMI EIKYU, YUKIO NISHIDA
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Publication number: 20010036714Abstract: Both P type and N type impurities are implanted from a plurality of directions. The tilt angle &thgr; of the implantation direction against the normal of the main surface of a semiconductor substrate is fixed to 10°, and the deflection angle &phgr; is set to such four directions (X, X+90°, X+180°, and X+270°, where X is an arbitrary angle) that projecting components of a vector indicating the implantation direction are opposed to each other on two lines that cross each other at right angles along the main surface of the semiconductor substrate. Thereby, the dependency of the breakdown voltage of element isolation on the direction of a well boundary is suppressed to realize a high breakdown voltage of element isolation in all directions.Type: ApplicationFiled: April 30, 2001Publication date: November 1, 2001Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Takeshi Kitani, Katsumi Eikyu, Masao Sugiyama
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Patent number: 5845105Abstract: A method of manufacturing a semiconductor device wherein the device is manufactured according to extracted process parameters. The process parameters are extracted as a set of optimum process parameters which satisfy an intended specification using process functions. The process functions describe a characteristic of the semiconductor device, and are determined using experimental values and/or simulated values. The process parameters may then be transmitted online to a factory.Type: GrantFiled: November 1, 1995Date of Patent: December 1, 1998Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Tatsuya Kunikiyo, Katsumi Eikyu, Kenichiro Sonoda, Masato Fujinaga, Kiyoshi Ishikawa, Norihiko Kotani