Abstract: A bus management node 11 has a register for channels in use REG1 and a bus capacity register REG2. Before starting the synchronous communication, each node 12 transmits a read-out command to the register for channels in use REG1 and the register for channels in use REG1 in order to read out their contents for ascertaining the number of the un-used channel and the residual capacity. If there is any un-used channel and any residual bus capacity, the node 12 transmits write commands to these registers REG1 and REG2 so that the number of the channel to be in use and the capacity of the bus to be in use will be stored in the register for channels in use REG1 and the bus capacity register REG2. This enables bus management to be achieved easily in a system performing synchronous communication between plural nodes connected to the bus.

Abstract: A bus management node 11 has a register for channels in use REG1 and a bus capacity register REG2. Before starting the synchronous communication, each node 12 transmits a read-out command to the register for channels in use REG1 and the register for channels in use REG1 in order to read out their contents for ascertaining the number of the un-used channel and the residual capacity. If there is any un-used channel and any residual bus capacity, the node 12 transmits write commands to these registers REG1 and REG2 so that the number of the channel to be in use and the capacity of the bus to be in use will be stored in the register for channels in use REG1 and the bus capacity register REG2. This enables bus management to be achieved easily in a system performing synchronous communication between plural nodes connected to the bus.

Abstract: In an input circuit for semiconductor devices, such as an address buffer, an arrangement is provided which obviates the timing margin from capture of an input signal to its latching and outputting, thereby increasing the operation speed of the input circuit. The address buffer includes a differential amplifier Ai which receives an input signal Ai and outputs a pair of differential signals A-come-first-served latch circuit detects, latches and outputs one of the paired differential signals that has changed first. Activation/inactivation of the differential amplifier is done by turning on and off an N-channel MOS transistor through a Set signal. When activated, the differential amplifier generates a potential difference between the paired differential signals and, when inactivated, has its paired differential signals go low.

Abstract: A bus management node 11 has a register for channels in use REG1 and a bus capacity register REG2. Before starting the synchronous communication, each node 12 transmits a read-out command to the register for channels in use REG1 and the register for channels in use REG1 in order to read out their contents for ascertaining the number of the un-used channel and the residual capacity If there is any un-used channel and any residual bus capacity, the node 12 transmits write commands to these registers REG1 and REG2 so that the number of the channel to be in use and the capacity of the bus to be in use will be stored in the register for channels in use REG1 and the bus capacity register REG2. This enables bus management to be achieved easily in a system performing synchronous communication between plural nodes connected to the bus.

Abstract: A data demultiplexer includes a write controller, a memory, an analyzing processing unit, and transfer control units. The write controller writes packets which have arrived thereat into the memory in the order of arrival and sends the write information to the analyzing processing unit. The analyzing processing unit analyzes packets in the order of arrival on the basis of the write information and sends only the result of analysis to the transfer control units. On the basis of the result of analysis, the transfer control units send data read from the memory in the order of packet arrival to the decoder. A data demultiplexer capable of reducing the processing in the analyzing processing unit can be provided.

Abstract: A semiconductor memory device capable of simultaneously providing volatile and non-volatile portions is disclosed having a plurality of memory mats, and a plurality of plate electrodes and a plurality of memory mats each provided in one-to-one correspondence with the memory maps. The memory mats each include a plurality of word lines, a plurality of bit lines and a plurality of memory cells provided at the intersections of the word lines and the bit lines. The memory cells each include an information storage capacitor having a ferroelectric film, and an address selection MOSFET. The information storage capacitor has a pair of electrodes, one of which is connected to the plate electrode that corresponds to the memory mat in which the information storage capacitor is included. A first voltage or a second voltage is selectively applied to each of the plate electrodes according to data held in the memory circuit corresponding to the plate electrode.

Abstract: A memory system is provided which is capable of eliminating deterioration in a processing rate due to possible signal delays between an input/output circuit and memory blocks. Complication of design is also reduced, especially when the scale and chip area of the memory system increase. A memory chip includes a plurality of memory array blocks each including an address buffer and an address counter, and operates on the basis of a local clock cycle. A control circuit is synchronous with a clock of an external device, and synchronous data-transfer circuitry includes a buffer which modulates the transfer rate of serial data which arrives from a memory array block at a local clock cycle so as to be synchronous with the clock of the control circuit. External clock signal lines are not distributed to the memory array blocks.

Abstract: A semiconductor memory which includes a plurality of memory cells each having first and second capacitors connected in series and a field-effect transistor whose source or drain is connected to a node between the first and second capacitors. The memory cells are arranged at intersections of bit lines and word lines thereby forming a matrix. The first capacitor of each memory cell is a ferroelectric capacitor using a ferroelectric material as an insulating film. A plate electrode of the first capacitor of each memory cell is held at a first potential when the memory is operated in a first mode and the plate electrode of the first capacitor is held at a second potential when the memory is operated in a second mode. The first potential is different from the second potential.

Abstract: A highly reliable and high speed ferroelectric memory having a high degree of integration. In a ferroelectric memory having a multiple of memory cells M1, each constituted by one transistor and one ferroelectric capacitor, in the normal operation, the ferroelectric memory is used as a volatile memory in which a voltage on a storage node ST1 stores information in a DRAM mode. Both the electric potential at the plate PL1 of the ferroelectric capacitor and a precharge electric potential on a data line DL1(j) are Vcc/2. When the a power supply voltage is turned on, a polarization state is detected as a ferroelectric memory of a plate electric potential of Vcc/2 and a precharge electric potential of Vss (or Vcc) and the read operation is performed a FERAM mode.

Abstract: A method of testing an electronic apparatus which eliminates a control signal line for setting an integrated circuit to a test mode and a test mode select terminal of an external terminal section and wherein fetching of test data and transfer of the thus fetched test data are performed in an integrated operation. In each of the integrated circuits, a boundary scan control circuit discriminates a category code at the top of data inputted from a serial input terminal to control a pair of switching circuits. When the category code represents a test mode, predetermined terminals of the switching circuits are selected so that input data are sent out to boundary scan cells. Fetching of parallel data from parallel input terminals and transfer to the boundary scan cells are performed at a time.

Abstract: A highly reliable and high speed ferroelectric memory having high degree of integration is provided. In a ferroelectric memory having a plurality of memory cells M1 each constituted by one transistor and one ferroelectric capacitor. In the normal operation, the ferroelectric memory is used as a volatile memory in which a voltage of a storage node ST1 is utilized as the stored information. Both an electric potential at a plate PL1 of the ferroelectric capacitor and a precharge electric potential on a data line DL1(j) are made Vcc/2.

Abstract: An integrated circuit for boundary scan is achieved to be simple structure. A testing apparatus 6 provides a testing data to a serial input port SI of a integrated circuit IC1 via a external terminal unit 2. The testing data is output to a parallel input port PI of the integrated circuit IC2 from a parallel output port SO of the integrated circuit IC1, then the testing data is output from the serial output port SO. The testing apparatus 6 compares with the testing data outputted to the integrated circuit IC1 and the testing data outputted from the integrated circuit IC2 so that a state of connection is detected between the parallel output port PO of the integrated circuit IC1 and the parallel input port PI of the integrated circuit IC2. The construction of the integrated circuits can be simplified by using both of inputting and outputting of the serial interface SIF.

Abstract: A mode processing circuit for a multi-operation mode electronic apparatus including a mode stack having a plurality of stages in which an input command signal is stored as an operation mode of the multi-operation mode electronic apparatus, wherein the operation mode inputted to the mode stack is sequentially stored and optimized and the optimized operation mode is read out from the mode stack in the sequential order and then executed after the transition of the operation mode is ended.