Abstract: A semiconductor chip includes a substrate, an electrode pad formed on the substrate, an insulating layer covering the substrate and the electrode pad, and having an opening exposing a portion of a surface of the electrode pad, a first conductive layer formed on the exposed portion of the surface of the electrode pad and extending to a surface of the insulating layer, and a second conductive layer formed on the first conductive layer, covering the first conductive layer in a plan view, and having an outer edge portion which is located further out than an outer edge of the first conductive layer in a plan view. The outer edge portion of the second conductive layer has at least one curved portion. At least one portion of the curved portion is located between the outer edge of the first conductive layer and an outer edge of the second conductive layer in a plan view.

Abstract: A semiconductor chip includes a substrate, an electrode pad formed on the substrate, an insulating layer covering the substrate and the electrode pad, and having an opening exposing a portion of a surface of the electrode pad, a first conductive layer formed on the exposed portion of the surface of the electrode pad and extending to a surface of the insulating layer, and a second conductive layer formed on the first conductive layer, covering the first conductive layer in a plan view, and having an outer edge portion which is located further out than an outer edge of the first conductive layer in a plan view. The outer edge portion of the second conductive layer has at least one curved portion. At least one portion of the curved portion is located between the outer edge of the first conductive layer and an outer edge of the second conductive layer in a plan view.

Abstract: A semiconductor chip includes a substrate, an electrode pad formed on the substrate, an insulating layer covering the substrate and the electrode pad, and having an opening exposing a portion of a surface of the electrode pad, a first conductive layer formed on the exposed portion of the surface of the electrode pad and extending to a surface of the insulating layer, and a second conductive layer formed on the first conductive layer, covering the first conductive layer in a plan view, and having an outer edge portion which is located further out than an outer edge of the first conductive layer in a plan view. The outer edge portion of the second conductive layer has at least one curved portion. At least one portion of the curved portion is located between the outer edge of the first conductive layer and an outer edge of the second conductive layer in a plan view.

Abstract: A semiconductor chip includes a substrate, an electrode pad formed on the substrate, an insulating layer covering the substrate and the electrode pad, and having an opening exposing a portion of a surface of the electrode pad, a first conductive layer formed on the exposed portion of the surface of the electrode pad and extending to a surface of the insulating layer, and a second conductive layer formed on the first conductive layer, covering the first conductive layer in a plan view, and having an outer edge portion which is located further out than an outer edge of the first conductive layer in a plan view. The outer edge portion of the second conductive layer has at least one curved portion. At least one portion of the curved portion is located between the outer edge of the first conductive layer and an outer edge of the second conductive layer in a plan view.

Abstract: A semiconductor device includes a semiconductor chip, a wiring on the chip, an insulating film coating the wiring and having an opening partially exposing the wiring, a Ti/W film on a portion of the wiring facing the opening, a Cu layer on the Ti/W film and the wiring's exposed portion, and having a peripheral edge protruding away from the opening more than Ti/W film's peripheral edge in parallel to an insulating film surface, and a solder ball bonded to the Cu layer. The protrusion of the Cu layer's peripheral edge with respect to the Ti/W film's peripheral edge is greater than the Ti/W film's thickness. The Ti/W film's surface doesn't vertically surpass the Cu layer's upper surface in the opening's center. A Cu layer/solder ball interface is arc-shaped on both sides of the Cu layer's upper surface in a cross section taken perpendicularly to the Cu layer's upper surface.

Abstract: A semiconductor device includes a semiconductor chip, a wiring on the chip, an insulating film coating the wiring and having an opening partially exposing the wiring, a Ti/W film on a portion of the wiring facing the opening, a Cu layer on the Ti/W film and the wiring's exposed portion, and having a peripheral edge protruding away from the opening more than Ti/W film's peripheral edge in parallel to an insulating film surface, and a solder ball bonded to the Cu layer. The protrusion of the Cu layer's peripheral edge with respect to the Ti/W film's peripheral edge is greater than the Ti/W film's thickness. The Ti/W film's surface doesn't vertically surpass the Cu layer's upper surface in the opening's center. A Cu layer/solder ball interface is arc-shaped on both sides of the Cu layer's upper surface in a cross section taken perpendicularly to the Cu layer's upper surface.

Abstract: A semiconductor device includes a semiconductor chip, a wiring formed on the semiconductor chip, a passivation film coating the wiring and having an opening for partially exposing the wiring from the passivation film an interposing film formed on a portion of the wiring and facing the opening, and a post bump raisedly formed on the interposing film and with a peripheral edge portion thereof protruding away from the opening more than a peripheral edge of the interposing film in a direction parallel to a surface of the passivation film.

Abstract: A semiconductor device according to the present invention includes: a semiconductor substrate; a first copper interconnection provided on the semiconductor substrate; an insulating layer provided over the first copper interconnection and having a hole extending therethrough to the first copper interconnection; a barrier layer composed of a tantalum-containing material and covering at least a sidewall of the hole and a part of the first copper interconnection exposed in the hole; and a second copper interconnection provided in intimate contact with the barrier layer and electrically connected to the first copper interconnection via the barrier layer; wherein the barrier layer has a nitrogen concentration profile such that the concentration of nitrogen contained in the material varies to be lower in a boundary portion of the barrier layer adjacent to the first copper interconnection and in a boundary portion of the barrier layer adjacent to the second copper interconnection and higher in an intermediate portion

Abstract: A semiconductor device according to the present invention includes: a semiconductor substrate; a first copper interconnection provided on the semiconductor substrate; an insulating layer provided over the first copper interconnection and having a hole extending therethrough to the first copper interconnection; a barrier layer composed of a tantalum-containing material and covering at least a sidewall of the hole and a part of the first copper interconnection exposed in the hole; and a second copper interconnection provided in intimate contact with the barrier layer and electrically connected to the first copper interconnection via the barrier layer; wherein the barrier layer has a nitrogen concentration profile such that the concentration of nitrogen contained in the material varies to be lower in a boundary portion of the barrier layer adjacent to the first copper interconnection and in a boundary portion of the barrier layer adjacent to the second copper interconnection and higher in an intermediate portion

Abstract: A plating apparatus has a frame configured to be placed on a substrate so that a plating bath is formed by the frame and the substrate. The frame includes a conductive core and a seal member covering the conductive core. The plating apparatus also has a non-conductive porous member configured to be immersed in an electrolytic plating solution held in the plating bath, a counter electrode disposed on the non-conductive porous member so as to face the substrate with a predetermined distance from the substrate, and a feed contact configured to be brought into contact with a peripheral portion of the substrate outside of the frame. The plating apparatus includes a power source operable to apply a voltage between the counter electrode and the substrate and a potential adjuster operable to control a potential of the conductive core of the frame with respect to a potential of the substrate.

Abstract: A semiconductor device according to the present invention includes: a semiconductor chip; a wiring formed on the semiconductor chip; a passivation film, coating the wiring and having an opening for partially exposing the wiring from the passivation film; an interposing film, formed on a portion of the wiring facing the opening; and a post bump, raisedly formed on the interposing film and with a peripheral edge portion thereof protruding more toward a side than a peripheral edge of the interposing film.

Abstract: A semiconductor chip including a bump projecting from a surface protective film thereof and a surface interconnection having a smaller height than the bump. The surface interconnection may project from the surface protective film or may be flush with the surface protective film. The surface interconnection may be connected to the bump. The bump may include a peripheral bump configured as surrounding a device formation region of the chip. The peripheral bump may be connected to the ground or a power source.

Abstract: A substrate holding apparatus can accurately control temperature of a substrate in a direct manner with a relatively simple arrangement. The substrate holding apparatus has a top ring configured to hold a substrate to be polished and press the substrate against a polishing surface, and an air bag attached to the top ring so as to be brought into contact with a rear face of the substrate. The substrate holding apparatus also has a regulator operable to regulate a temperature control fluid to be supplied into the air bag, and a flow regulating valve operable to regulate a flow rate of the temperature control fluid discharged from the air bag.

Abstract: A method to quantitatively detect an optimum endpoint of dressing of a polishing pad with a non-destructive monitoring of a surface of the polishing pad is offered. The polishing pad is dressed for a predetermined period, and roughness of the surface of the polishing pad is measured with an optical measurement device made of a laser focus displacement meter. Then a characteristic curve representing a correlation between surface roughness of the polishing pad and dressing time is obtained. A gradient of the surface roughness versus dressing time characteristic curve is obtained. Dressing is stopped when the gradient reaches a predetermined value of gradient. These steps are repeated until the gradient of the surface roughness versus dressing time characteristic curve reaches the predetermined value of gradient.

Abstract: A semiconductor chip having a functional bump provided on a surface of a semiconductor substrate thereof for electrical connection between an internal circuit thereof and a solid device, and a dummy bump not serving for the electrical connection between the internal circuit and the solid device. The dummy bump may be a stress relieving bump for relieving stresses exerted thereon. The dummy bump may be connected to a low impedance portion. The functional bump and the dummy bump may be provided on a surface protective film. In this case, the dummy bump is provided on a recess formed in the surface protective film.

Abstract: A plating apparatus can form a plated film having a uniform thickness on a surface to be plated of a substrate without employing a complicated structure, such as a conduction detection means capable of detecting the state of conduction (contact state) of feeding contacts in contact with a conductive portion of the substrate. The plating apparatus includes a substrate holder having a plurality of feeding contacts for contact with a conductive portion provided in a surface of a substrate, wherein the substrate holder includes a feeding ring comprised of a single member and having the feeding contacts disposed at regular intervals along the circumferential direction, a plurality of substrate chucks for contact with the substrate in the vicinity of the contact portions of the feeding contacts with the conductive portion to support the substrate, and a substrate deflection preventing mechanism for preventing deflection of the substrate.

Abstract: A plating apparatus has a frame configured to be placed on a substrate so that a plating bath is formed by the frame and the substrate. The frame includes a conductive core and a seal member covering the conductive core. The plating apparatus also has a non-conductive porous member configured to be immersed in an electrolytic plating solution held in the plating bath, a counter electrode disposed on the non-conductive porous member so as to face the substrate with a predetermined distance from the substrate, and a feed contact configured to be brought into contact with a peripheral portion of the substrate outside of the frame. The plating apparatus includes a power source operable to apply a voltage between the counter electrode and the substrate and a potential adjuster operable to control a potential of the conductive core of the frame with respect to a potential of the substrate.

Abstract: A substrate holding apparatus can accurately control temperature of a substrate in a direct manner with a relatively simple arrangement. The substrate holding apparatus has a top ring configured to hold a substrate to be polished and press the substrate against a polishing surface and an air bag attached to the top ring so as to be brought into contact with a rear face of the substrate. The substrate holding apparatus also has a regulator operable to regulate a temperature control fluid to be supplied into the air bag and a flow regulating valve operable to regulate a flow rate of the temperature control fluid discharged from the air bag.

Abstract: Ferroelectric memory includes a hollow formed in a first insulation film. A lower electrode is formed in this hollow by sol-gel method including an application process due to a spin coat method. In this application process, a precursor solution is dripped on a surface of the first insulation film and splashed away due to centrifugal force. Due to this, a first conductive film to being formed has an increased film thickness at portion of the hollow where the precursor solution is ready to correct, or portion to be formed into a lower electrode, and a decreased film thickness at portion other than the hollow. Accordingly, it is satisfactory to etch only the hollow portion when forming a lower electrode by dry-etching the first conductive film.

Abstract: A method to quantitatively detect an optimum endpoint of dressing of a polishing pad with a non-destructive monitoring of a surface of the polishing pad is offered. The polishing pad is dressed for a predetermined period, and roughness of the surface of the polishing pad is measured with an optical measurement device made of a laser focus displacement meter. Then a characteristic curve representing a correlation between surface roughness of the polishing pad and dressing time is obtained. A gradient of the surface roughness versus dressing time characteristic curve is obtained. Dressing is stopped when the gradient reaches a predetermined value of gradient. These steps are repeated until the gradient of the surface roughness versus dressing time characteristic curve reaches the predetermined value of gradient.