Patents by Inventor Katsumi Taniguchi

Katsumi Taniguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240071900
    Abstract: A semiconductor device includes: a resin insulated substrate including a first rein insulating layer, a conductor base provided on one of main surfaces of the first resin insulating layer, and a conductor foil provided on another main surface of the first resin insulating layer; a power semiconductor element bonded to the conductor foil; a case surrounding an outer circumference of the resin insulated substrate; a sealing resin provided inside the case to seal the power semiconductor element; and a second resin insulating layer provided between the first resin insulating layer and the sealing resin and having a lower water-absorption rate than the sealing resin.
    Type: Application
    Filed: June 28, 2023
    Publication date: February 29, 2024
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Katsumi TANIGUCHI
  • Patent number: 11905196
    Abstract: A mold for manufacturing a quartz glass crucible by a rotary molding method, having a plurality of grooves that are concentric with respect to a mold rotation axis in at least a straight body portion of an inner surface of the mold, wherein the plurality of concentric grooves are non-penetrating grooves that do not penetrate the mold. This provides a mold for manufacturing a quartz glass crucible by a rotary molding method, having an inner surface made so that it is difficult for quartz powder to slide down when forming a quartz powder compact.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: February 20, 2024
    Assignee: SHIN-ETSU QUARTZ PRODUCTS CO., LTD.
    Inventors: Jiro Sawazaki, Yasuo Ohama, Katsumi Taniguchi
  • Publication number: 20230187334
    Abstract: A semiconductor device includes: an insulating sheet including a first main surface and a second main surface; a first terminal in a shape of a plate provided to face the first main surface of the insulating sheet and including a first protruding portion protruding outward from the first main surface of the insulating sheet; and a second terminal in a shape of a plate provided to face the second main surface of the insulating sheet and including a second protruding portion protruding outward from the second main surface of the insulating sheet side by side with the first protruding portion, wherein a first recessed portion is provided at a position of the first protruding portion intersecting an end portion of the insulating sheet by concaving a side surface of the first protruding portion facing the second protruding portion in a direction away from the second protruding portion.
    Type: Application
    Filed: October 27, 2022
    Publication date: June 15, 2023
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Yuma MURATA, Katsumi TANIGUCHI, Ryoichi KATO
  • Publication number: 20230124778
    Abstract: A semiconductor module (semiconductor device) includes a case that has a side wall to form a frame, the side wall having a concave portion, a multi-layer structure in which a first terminal, an insulating sheet, and a second terminal are stacked in that order and which is disposed on the concave portion, and a beam member that is attached to the concave portion of the case to fix the multi-layer structure disposed on the concave portion.
    Type: Application
    Filed: September 27, 2022
    Publication date: April 20, 2023
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Akito NAKAGOME, Katsumi TANIGUCHI, Ryoichi KATO, Yuma MURATA
  • Publication number: 20230119240
    Abstract: A semiconductor device includes: an insulated circuit substrate; a power semiconductor element mounted on the insulated circuit substrate; a first terminal having a plate-like shape having a first main surface and electrically connected to the power semiconductor element; a second terminal having a second main surface opposed to the first main surface of the first terminal and electrically connected to the power semiconductor element; an insulating sheet interposed between the first main surface and the second main surface; and a conductive film provided on at least one of the first main surface side and the second main surface side of the insulating sheet.
    Type: Application
    Filed: August 24, 2022
    Publication date: April 20, 2023
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Katsumi TANIGUCHI, Yoshinari IKEDA, Ryoichi KATO, Yuma MURATA, Akito NAKAGOME
  • Patent number: 11201121
    Abstract: A semiconductor device encompasses a cooler made of ceramics, having a first main face and a second main face, being parallel and opposite to the first main face, defined by two opposite side faces perpendicular to the first and second main faces, a plurality of conductive-pattern layers delineated on the first main face, a semiconductor chip mounted on the first main face via one of the plurality of conductive-pattern layers, and a seal member configured to seal the semiconductor chip.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: December 14, 2021
    Assignee: FUJI ELECTRIC CO., LTD
    Inventors: Kohei Yamauchi, Hiromichi Gohara, Ryoichi Kato, Yoshinari Ikeda, Katsumi Taniguchi
  • Publication number: 20210257269
    Abstract: A semiconductor device having a base circuit board, a case surrounding the base circuit board to demarcate, in a plan view, an opening area in which the base circuit board is disposed, and a sealing member that seals the base circuit board disposed in the case. The base circuit board includes a metal base substrate, a resin layer formed on the metal base substrate, and a circuit pattern formed on the resin layer. The case has an inner wall surface that faces an outer peripheral side surface of the base circuit board, and that includes a first inner wall portion which is in surface contact with an outer peripheral side surface of the metal base substrate, and a second inner wall portion that is separate from the outer peripheral side surface of the base circuit board, to thereby have a first gap therebetween filled with the sealing member.
    Type: Application
    Filed: January 25, 2021
    Publication date: August 19, 2021
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Katsumi TANIGUCHI
  • Patent number: 11056475
    Abstract: A semiconductor module includes: a first circuit substrate having a conductive layer disposed on an insulating plate; a plurality of semiconductor elements on the conductive layer, a second circuit substrate disposed above the semiconductor elements, the second circuit substrate having a main current wiring layer and a control wiring layer positioned in a layer above the main current wiring layer; a first lead terminal vertically extending upwards from and in contact with the main current wiring layer; a second lead terminal vertically extending upwards from and in contact with the conductive layer of the first circuit substrate; a third lead terminal vertically extending upwards from and in contact with the control wiring layer; and a sealing material covering at least some of the elements mentioned above.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: July 6, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Katsumi Taniguchi
  • Patent number: 10998309
    Abstract: A semiconductor unit includes: a plurality of transistor chips arranged in a plurality of parallel rows, each transistor chip respectively having a first main electrode on one surface and a second main electrode on another surface; a first conductor layer electrically connected to the first main electrodes of the transistor chips, both corner portions on one end of the first conductor layer being drawn out in a direction in which the rows of transistor chips run; a second conductor layer arranged between the both corner portions of the first conductor layer; and a wiring substrate that is arranged on a side of the second main electrodes of the plurality of transistor chips and includes a wiring layer electrically connected to the second main electrodes of the plurality of transistor chips and to the second conductor layer.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: May 4, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Masashi Hoya, Katsumi Taniguchi, Naoyuki Kanai
  • Patent number: 10971431
    Abstract: A semiconductor device includes: a first cooling device including a plurality of first flow channels through which a fluid flows, between a first main surface and a second main surface opposed to each other; a second cooling device including a plurality of second flow channels through which a fluid flows, between a third main surface and a fourth main surface parallel to the first main surface; a semiconductor element interposed between the first main surface and the third main surface facing each other; and a control terminal penetrating from the third main surface to the fourth main surface in a terminal-penetrating region defined at a predetermined position between the plurality of second flow channels, and electrically connected to a control electrode of the semiconductor element.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: April 6, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Kohei Yamauchi, Hiromichi Gohara, Katsumi Taniguchi
  • Patent number: 10910324
    Abstract: A semiconductor device has a configuration in which a stacked assembly and a resin case are combined. The stacked assembly includes a semiconductor element, a stacked substrate on which the semiconductor element is mounted, and a metal substrate on which the stacked substrate is mounted. In the resin case, a notch groove is provided at a corner portion for reducing a stress. At least one of a width and a length of the notch groove is 2 mm or more.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: February 2, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Tatsuhiko Asai, Katsumi Taniguchi
  • Publication number: 20200399160
    Abstract: A mold for manufacturing a quartz glass crucible by a rotary molding method, having a plurality of grooves that are concentric with respect to a mold rotation axis in at least a straight body portion of an inner surface of the mold, wherein the plurality of concentric grooves are non-penetrating grooves that do not penetrate the mold. This provides a mold for manufacturing a quartz glass crucible by a rotary molding method, having an inner surface made so that it is difficult for quartz powder to slide down when forming a quartz powder compact.
    Type: Application
    Filed: December 4, 2018
    Publication date: December 24, 2020
    Applicant: SHIN-ETSU QUARTZ PRODUCTS CO., LTD.
    Inventors: Jiro SAWAZAKI, Yasuo OHAMA, Katsumi TANIGUCHI
  • Patent number: 10825746
    Abstract: The present invention includes: a plurality of semiconductor modules on a metal base (conductor base); a first insulating bus bar and a second insulating bus bar connecting the semiconductor modules; a box-like insulating resin frame around the semiconductor modules; a first insulating layer that seals the semiconductor modules, the first insulating layer having an upper surface at a position that is lower than upper ends of terminals extending from an insulating circuit substrate of the semiconductor module inside the insulating resin frame; and second insulating layers on the first insulating layer inside the insulating resin frame, the upper ends of the terminals being buried inside the second insulating layers. Interfaces formed by the first insulating layer, second insulating layers, and sidewall parts (third insulating layer) of the insulating resin frame are arranged between the terminals and ground positions formed at the lower ends of the sidewall parts.
    Type: Grant
    Filed: April 5, 2019
    Date of Patent: November 3, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Katsumi Taniguchi
  • Publication number: 20200091140
    Abstract: A semiconductor unit includes: a plurality of transistor chips arranged in a plurality of parallel rows, each transistor chip respectively having a first main electrode on one surface and a second main electrode on another surface; a first conductor layer electrically connected to the first main electrodes of the transistor chips, both corner portions on one end of the first conductor layer being drawn out in a direction in which the rows of transistor chips run; a second conductor layer arranged between the both corner portions of the first conductor layer; and a wiring substrate that is arranged on a side of the second main electrodes of the plurality of transistor chips and includes a wiring layer electrically connected to the second main electrodes of the plurality of transistor chips and to the second conductor layer.
    Type: Application
    Filed: September 10, 2019
    Publication date: March 19, 2020
    Applicant: Fuji Electric Co., Ltd.
    Inventors: Masashi HOYA, Katsumi TANIGUCHI, Naoyuki KANAI
  • Publication number: 20200091130
    Abstract: A semiconductor module includes: a first circuit substrate having a conductive layer disposed on an insulating plate; a plurality of semiconductor elements on the conductive layer, a second circuit substrate disposed above the semiconductor elements, the second circuit substrate having a main current wiring layer and a control wiring layer positioned in a layer above the main current wiring layer; a first lead terminal vertically extending upwards from and in contact with the main current wiring layer; a second lead terminal vertically extending upwards from and in contact with the conductive layer of the first circuit substrate; a third lead terminal vertically extending upwards from and in contact with the control wiring layer; and a sealing material covering at least some of the elements mentioned above.
    Type: Application
    Filed: September 4, 2019
    Publication date: March 19, 2020
    Applicant: Fuji Electric Co., Ltd.
    Inventor: Katsumi TANIGUCHI
  • Patent number: 10531557
    Abstract: A wireless module includes a substrate that includes a first portion, a second portion, and a first flexible portion connecting the first portion and the second portion to each other. The first portion includes a circuit element that is mounted on the first main surface and a circuit including at least the circuit element. The second portion includes a first coil connected to the circuit. The first portion and the second portion face each other. A magnetic sheet is disposed on a second main surface of the second portion, and a battery is disposed between the second main surface of the first portion and the magnetic layer.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: January 7, 2020
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Takafumi Nasu, Tatsuya Hosotani, Katsumi Taniguchi, Makoto Takeoka, Masaaki Kanao
  • Patent number: 10529642
    Abstract: The semiconductor device includes a first conductive layer, semiconductor elements bonded to the upper surface of the first conductive layer, a second conductive layer separated from the first conductive layer, a control terminal bonded to the second conductive layer, a control resistor bonded to the upper surface of the second conductive layer, a control-resistor pin bonded to the upper surface of the control resistor and a wiring board having a control-wiring layer for electrically connecting the semiconductor elements and the control-resistor pin.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: January 7, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Katsumi Taniguchi, Motohito Hori
  • Publication number: 20190371705
    Abstract: A semiconductor device includes: a first cooling device including a plurality of first flow channels through which a fluid flows, between a first main surface and a second main surface opposed to each other; a second cooling device including a plurality of second flow channels through which a fluid flows, between a third main surface and a fourth main surface parallel to the first main surface; a semiconductor element interposed between the first main surface and the third main surface facing each other; and a control terminal penetrating from the third main surface to the fourth main surface in a terminal-penetrating region defined at a predetermined position between the plurality of second flow channels, and electrically connected to a control electrode of the semiconductor element.
    Type: Application
    Filed: March 22, 2019
    Publication date: December 5, 2019
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Kohei YAMAUCHI, Hiromichi Gohara, Katsumi Taniguchi
  • Publication number: 20190355632
    Abstract: The present invention includes: a plurality of semiconductor modules on a metal base (conductor base); a first insulating bus bar and a second insulating bus bar connecting the semiconductor modules; a box-like insulating resin frame around the semiconductor modules; a first insulating layer that seals the semiconductor modules, the first insulating layer having an upper surface at a position that is lower than upper ends of terminals extending from an insulating circuit substrate of the semiconductor module inside the insulating resin frame; and second insulating layers on the first insulating layer inside the insulating resin frame, the upper ends of the terminals being buried inside the second insulating layers. Interfaces formed by the first insulating layer, second insulating layers, and sidewall parts (third insulating layer) of the insulating resin frame are arranged between the terminals and ground positions formed at the lower ends of the sidewall parts.
    Type: Application
    Filed: April 5, 2019
    Publication date: November 21, 2019
    Applicant: Fuji Electric Co., Ltd.
    Inventor: Katsumi TANIGUCHI
  • Patent number: 10374304
    Abstract: An electronic apparatus includes an antenna device, a circuit board, and a housing containing the antenna device and the circuit board. The inner surface of the housing is spaced apart from the circuit board. The antenna device includes an antenna unit, a matching circuit unit connected to the antenna unit, a transmission line unit connected to the matching circuit unit, and a connecting portion included in the transmission line unit. The antenna device is disposed along the inner surface of the housing. The connecting portion is connected to a circuit of the circuit board. The antenna device includes a ground connection portion in the matching circuit unit in a region where the antenna device is disposed along the inner surface of the housing. The ground connection portion electrically connects a second ground conductor of the antenna device to a first ground conductor on the housing.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: August 6, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Katsumi Taniguchi, Noboru Kato