Patents by Inventor Katsumi Yamamoto

Katsumi Yamamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210215722
    Abstract: A measurement method and a measurement reagent for thyroglobulin, which enable measurement of a more accurate amount of thyroglobulin by a single test without being influenced by interference of anti-thyroglobulin antibody, are disclosed. The measurement method for thyroglobulin, wherein thyroglobulin in a sample separated from a body is measured by an immunoassay, includes a pretreatment step of mixing the sample separated from a body with a pretreatment liquid containing one or both of a surfactant and an acidifier. The reagent for immunoassay of thyroglobulin includes a pretreatment liquid containing one or both of a surfactant and an acidifier.
    Type: Application
    Filed: September 5, 2017
    Publication date: July 15, 2021
    Applicant: FUJIREBIO INC.
    Inventors: Kosuke YAMAMOTO, Yoshiyuki KITAMURA, Shintaro YAGI, Katsumi AOYAGI
  • Patent number: 10903238
    Abstract: A semiconductor device includes a substrate, a stacked body provided on the substrate, a first insulator dividing the stacked body in a second direction crossing the first direction, a second insulator adjacent to the first insulator and dividing the stacked body in the second direction, a first hole, and a first insulating member. In the stacked body, a plurality of layers are stacked in a first direction perpendicular to the upper surface of the substrate. The first hole penetrates the stacked body and the first insulator in the first direction. The first insulating member penetrates the stacked body and the second insulator in the first direction and is adjacent to the first hole via a first electrode in a third direction crossing the first direction and the second direction, and has an opening diameter larger than that of the first insulator.
    Type: Grant
    Filed: January 23, 2020
    Date of Patent: January 26, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Katsumi Yamamoto, Keisuke Kikutani
  • Publication number: 20200161331
    Abstract: A semiconductor device includes a substrate, a stacked body provided on the substrate, a first insulator dividing the stacked body in a second direction crossing the first direction, a second insulator adjacent to the first insulator and dividing the stacked body in the second direction, a first hole, and a first insulating member. In the stacked body, a plurality of layers are stacked in a first direction perpendicular to the upper surface of the substrate. The first hole penetrates the stacked body and the first insulator in the first direction. The first insulating member penetrates the stacked body and the second insulator in the first direction and is adjacent to the first hole via a first electrode in a third direction crossing the first direction and the second direction, and has an opening diameter larger than that of the first insulator.
    Type: Application
    Filed: January 23, 2020
    Publication date: May 21, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Katsumi YAMAMOTO, Keisuke KIKUTANI
  • Patent number: 10573660
    Abstract: A semiconductor device includes a substrate, a stacked body provided on the substrate, a first insulator dividing the stacked body in a second direction crossing the first direction, a second insulator adjacent to the first insulator and dividing the stacked body in the second direction, a first hole, and a first insulating member. In the stacked body, a plurality of layers are stacked in a first direction perpendicular to the upper surface of the substrate. The first hole penetrates the stacked body and the first insulator in the first direction. The first insulating member penetrates the stacked body and the second insulator in the first direction and is adjacent to the first hole via a first electrode in a third direction crossing the first direction and the second direction, and has an opening diameter larger than that of the first insulator.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: February 25, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Katsumi Yamamoto, Keisuke Kikutani
  • Patent number: 10559954
    Abstract: A calibration circuit may comprise a negative pack terminal, an intermediate node, and a first protection IC coupled to a first transistor. The first transistor may be coupled between the negative pack terminal and the intermediate node. The calibration circuit may comprise a second protection IC coupled in parallel with the first protection IC and further coupled to a second transistor. A power source may be coupled in parallel with the first and second protection ICs, and a current source may be coupled between the negative pack terminal and the intermediate node, wherein the intermediate node is positioned between the first transistor and the second transistor, and the power source is configured to provide a current to the first protection IC through a first current loop.
    Type: Grant
    Filed: April 4, 2017
    Date of Patent: February 11, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Atsushi Kamei, Yasuaki Hayashi, Katsumi Yamamoto
  • Publication number: 20190379202
    Abstract: A battery apparatus according to various aspects of the present invention may operate in conjunction with a power source, such as a battery. The battery apparatus may include a protection IC, a first terminal, a second terminal, and a third terminal. The power source may be selectively coupled to the battery apparatus at the second and third terminals. The power source may be capable of providing a current through the battery apparatus via one of a first current loop and a second current loop.
    Type: Application
    Filed: August 20, 2019
    Publication date: December 12, 2019
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Atsushi KAMEI, Yasuaki HAYASHI, Katsumi YAMAMOTO
  • Publication number: 20190296036
    Abstract: A semiconductor device includes a substrate, a stacked body provided on the substrate, a first insulator dividing the stacked body in a second direction crossing the first direction, a second insulator adjacent to the first insulator and dividing the stacked body in the second direction, a first hole, and a first insulating member. In the stacked body, a plurality of layers are stacked in a first direction perpendicular to the upper surface of the substrate. The first hole penetrates the stacked body and the first insulator in the first direction. The first insulating member penetrates the stacked body and the second insulator in the first direction and is adjacent to the first hole via a first electrode in a third direction crossing the first direction and the second direction, and has an opening diameter larger than that of the first insulator.
    Type: Application
    Filed: August 20, 2018
    Publication date: September 26, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Katsumi YAMAMOTO, Keisuke KIKUTANI
  • Patent number: 10418802
    Abstract: A calibration circuit according to various aspects of the present invention comprises a battery pack, a protection IC, and a power source. The power source may have a predetermined voltage and may be selectively coupled to the protection IC. The power source may be capable of providing a current to the protection IC through one of a first current loop and a second current loop, wherein the current through the first current loop generates a first voltage across a first and second terminal of the protection IC, and the current through the second current loop generates a second voltage across the first and second terminals that is substantially equal to the voltage of the power source.
    Type: Grant
    Filed: April 4, 2017
    Date of Patent: September 17, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Atsushi Kamei, Yasuaki Hayashi, Katsumi Yamamoto
  • Patent number: 10325920
    Abstract: A method for manufacturing a semiconductor device includes forming a first mask layer having a first opening on an underlying layer; forming a first layer in a space where the underlying layer is selectively removed via the first opening; forming a second mask layer on the first mask layer and the first layer, the second mask layer having a second opening crossing the first opening; and selectively removing the first layer at a portion where the first opening and the second opening cross. At least one of the first and second mask layers having openings including the first or second opening, the openings being arranged in the first mask layer along a first direction, and/or being arranged in the second mask layer along a second direction, the first opening crossing the second opening in the first direction, and the second opening crossing the first opening in the second direction.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: June 18, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Chihiro Abe, Keisuke Kikutani, Katsumi Yamamoto, Tomoya Oori
  • Publication number: 20180287374
    Abstract: A calibration circuit may comprise a negative pack terminal, an intermediate node, and a first protection IC coupled to a first transistor. The first transistor may be coupled between the negative pack terminal and the intermediate node. The calibration circuit may comprise a second protection IC coupled in parallel with the first protection IC and further coupled to a second transistor. A power source may be coupled in parallel with the first and second protection ICs, and a current source may be coupled between the negative pack terminal and the intermediate node, wherein the intermediate node is positioned between the first transistor and the second transistor, and the power source is configured to provide a current to the first protection IC through a first current loop.
    Type: Application
    Filed: April 4, 2017
    Publication date: October 4, 2018
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Atsushi KAMEI, Yasuaki HAYASHI, Katsumi YAMAMOTO
  • Publication number: 20180287373
    Abstract: A calibration circuit according to various aspects of the present invention comprises a battery pack, a protection IC, and a power source. The power source may have a predetermined voltage and may be selectively coupled to the protection IC. The power source may be capable of providing a current to the protection IC through one of a first current loop and a second current loop, wherein the current through the first current loop generates a first voltage across a first and second terminal of the protection IC, and the current through the second current loop generates a second voltage across the first and second terminals that is substantially equal to the voltage of the power source.
    Type: Application
    Filed: April 4, 2017
    Publication date: October 4, 2018
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Atsushi KAMEI, Yasuaki HAYASHI, Katsumi YAMAMOTO
  • Publication number: 20180086205
    Abstract: When start control is initiated, the start control device operates in a first operating mode in which an upper limit value of an engine speed is limited to a first upper limit value (NErev1) that is lower than an upper limit value (NErev0) in a non-start control. When an elapsed period of time after a throttle opening has exceeded a predetermined opening in the first operating mode reaches a predetermined standby time, the start control device operates in a second operating mode in which the upper limit value of the engine speed is limited to a second upper limit value (NErev2) that is lower than the first upper limit value. The start control device transitions to an ordinary mode to thereby terminate the start control when a period of time of the second operating mode reaches a predetermined control period of time or a forced cancellation condition holds.
    Type: Application
    Filed: September 25, 2017
    Publication date: March 29, 2018
    Inventors: Katsumi Koyama, Hideki Uematsu, Fuyuki Kobayashi, Isao Azumagakito, Katsumi Yamamoto, Kazumasa Ogino
  • Patent number: 9847342
    Abstract: A semiconductor memory device includes a first structural body, a second structural body and interconnections. The first and the second structural bodies are separated in a first direction and extend in a second direction. The interconnections are provided between the first structural body and the second structural body, extend in the second direction, and are separated from each other along a third direction. The first and the second structural bodies each includes an insulating member, a column-shaped body and an insulating film. The insulating member and the column-shaped body are disposed in an alternating manner along the second direction and extend in the third direction. The insulating members of the first and second structural bodies make contact with the interconnections.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: December 19, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Satoshi Nagashima, Katsumi Yamamoto, Kohei Sakaike, Tatsuya Kato, Keisuke Kikutani, Fumitaka Arai, Atsushi Murakoshi, Shunichi Takeuchi, Katsuyuki Sekine
  • Publication number: 20170330890
    Abstract: A method for manufacturing a semiconductor device includes forming a first mask layer having a first opening on an underlying layer; forming a first layer in a space where the underlying layer is selectively removed via the first opening; forming a second mask layer on the first mask layer and the first layer, the second mask layer having a second opening crossing the first opening; and selectively removing the first layer at a portion where the first opening and the second opening cross. At least one of the first and second mask layers having openings including the first or second opening, the openings being arranged in the first mask layer along a first direction, and/or being arranged in the second mask layer along a second direction, the first opening crossing the second opening in the first direction, and the second opening crossing the first opening in the second direction.
    Type: Application
    Filed: November 14, 2016
    Publication date: November 16, 2017
    Applicant: Toshiba Memory Corporation
    Inventors: Chihiro ABE, Keisuke KlKUTANI, Katsumi YAMAMOTO, Tomoya OORI
  • Publication number: 20170263619
    Abstract: A semiconductor memory device includes a first structural body, a second structural body and interconnections. The first and the second structural bodies are separated in a first direction and extend in a second direction. The interconnections are provided between the first structural body and the second structural body, extend in the second direction, and are separated from each other along a third direction. The first and the second structural bodies each includes an insulating member, a column-shaped body and an insulating film. The insulating member and the column-shaped body are disposed in an alternating manner along the second direction and extend in the third direction. The insulating members of the first and second structural bodies make contact with the interconnections.
    Type: Application
    Filed: September 16, 2016
    Publication date: September 14, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Satoshi NAGASHIMA, Katsumi YAMAMOTO, Kohei SAKAIKE, Tatsuya KATO, Keisuke KlKUTANI, Fumitaka ARAI, Atsushi MURAKOSHI, Shunichi TAKEUCHI, Katsuyuki SEKINE
  • Publication number: 20170033585
    Abstract: A battery reset system. Implementations may include: an embedded battery, a battery control circuit coupled with the embedded battery, a discharging field effect transistor (FET) coupled with the battery control circuit, and a charging FET coupled with the battery control circuit. The system may also include a positive battery terminal coupled with the battery and a negative battery terminal coupled with the embedded battery and a reset terminal coupled with a reset circuit coupled with the battery control circuit. The reset circuit and the battery control circuit may be included in a single semiconductor chip coupled with the discharging FET, charging FET, and embedded battery.
    Type: Application
    Filed: July 31, 2015
    Publication date: February 2, 2017
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Mutsuki NIKI, Keiji AMEMIYA, Yasuaki HAYASHI, Katsumi YAMAMOTO
  • Patent number: 9528550
    Abstract: A sliding bearing including: a lining; a back metal; and an intermediate layer formed between the back metal and the lining by an Al alloy containing 0.01 wt % or more of at least one solid solution component selected from Zn, Cu, Mg, Li, Mn, V, Zr, Fe, Mo, Co, Ni, Hf, Sc, Ti and W wherein the whole amount of the solid solution component forms a solid solution with Al, in such a manner that the intermediate layer has a thickness of 20 ?m or more and Vickers hardness of 30 or more and 80 or less.
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: December 27, 2016
    Assignee: TAIHO KOGYO CO., LTD.
    Inventor: Katsumi Yamamoto
  • Patent number: 9520322
    Abstract: A semiconductor device includes a semiconductor substrate including a first surface in which an integrated circuit and an I/O pad electrically connected to the integrated circuit are formed, and a second surface which is an opposite side to the first surface, where a two-stage through-hole is formed in the semiconductor substrate, the semiconductor substrate including a first shape portion having a tapered shape which has a wall surface and of which a diameter of an opening becomes smaller toward a bottom of the hole from the second surface side to a predetermined position of the semiconductor substrate in a thickness direction, and including a second shape portion having a cylindrical shape which extends from the first shape portion to the I/O pad on the first surface side, and that includes an inorganic insulating film which is formed on the wall surface of the two-stage through-hole and the second surface.
    Type: Grant
    Filed: July 2, 2014
    Date of Patent: December 13, 2016
    Assignee: TOPPAN PRINTING CO., LTD.
    Inventors: Kenta Hayashi, Katsumi Yamamoto, Makoto Nakamura, Naoyuki Akiyama, Kyosuke Taguchi
  • Patent number: 9514984
    Abstract: A method for manufacturing a semiconductor device includes forming an insulating layer on a semiconductor layer; forming a metal layer on the insulating layer; and forming a first interconnect by selectively etching the metal layer. The first interconnect is electrically connected to the semiconductor layer and has a loop configuration. The method includes forming a first mask layer covering the first interconnect and the insulating layer; and forming a second mask layer on the first mask layer. The second mask layer has a first opening over a portion of the first interconnect. The method further includes exposing the portion of the first interconnect by selectively removing the first mask layer using the second mask layer; and forming a second interconnect by selectively removing the portion of the first interconnect using the first mask layer. The second interconnect has two ends and is electrically connected to the semiconductor layer.
    Type: Grant
    Filed: February 1, 2016
    Date of Patent: December 6, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Katsumi Yamamoto
  • Publication number: 20160091021
    Abstract: To provide a technique by which the occurrence of cracks due to fatigue can be suppressed. The sliding bearing of the present invention is a sliding bearing including: a lining consisting of 3 wt % or more and 12.5 wt % or less of Sn, 1 wt % or more and 8 wt % or less of Si, 0.05 wt % or more and 3 wt % or less of Cr, 0.05 wt % or more and 0.3 wt % or less of Zr, 0.01 wt % or more and 0.5 wt % or less of Ti, 3 wt % or less of Cu or Mg, and 0 wt % or more and 9 wt % or less of Bi, and the balance Al with inevitable impurities, 10 wt % or more and 90 wt % or less of Cr forming an intermetallic compound with Al, and the rest of Cr forming a solid solution with Al; a back metal; and an intermediate layer formed between the back metal and the lining by an Al alloy containing 0.
    Type: Application
    Filed: March 13, 2015
    Publication date: March 31, 2016
    Applicant: TAIHO KOGYO CO., LTD.
    Inventor: Katsumi YAMAMOTO