Abstract: A microcomputer with a built-in flash memory includes a flash controller for controlling writing/erasing of the flash memory in accordance with a command from a CPU. The flash controller produces a CPU rewriting mode designating signal and a busy signal during writing/erasing of the flash memory. In response to the two signals, awaiting mode controller implements a waiting mode by outputting a control signal to open and close an AND gate using the control signal, thereby halting a supply of a clock signal to the CPU in the waiting mode. The microcomputer can reduce the load on software for writing/erasing of the flash memory, and the load on developing software.

Abstract: Data are written in a plurality of block areas of a one-time program ROM including a replaced block area having bugs, and correction data desired to be stored in the replaced block area is written in a replacing block area of the one-time program ROM. Bits indicating a block address of a replaced block area having bugs are written in a replaced address register. When bits indicating a block address of a currently accessed block area agrees with those of the replaced block area in an address comparator, the access to the replaced block area is inhibited, the replacing block area is accessed, and the correction data of the replaced block area is read out from the replacing block area in place of the replaced block area.

Abstract: A microcomputer comprises: a flash memory for storing rewriting control F/W and user S/F; a command register for specifying content of rewriting control; a address register to be subjected to rewriting-control; a data register for specifying data to be written; a power-supply pump circuit in the flash memory; and a control signal register for specifying/outputting a control signal to a memory decoder. A CPU of the microcomputer is capable of accessing these four registers to perform writing or reading. A given bit of the control signal register corresponds to a given control signal. A value written to the register becomes a control signal that will be directly supplied to both of the power supply circuit and the memory decoder, in the flash memory, to control them. By rewriting a set value of this control signal register using the rewriting control F/W according to a specified sequence, processing such as “erase” and “program” of the flash memory is performed.

Abstract: A microcomputer includes a flash memory, a central processing unit, a plurality of storage devices, and an address predecoder. The predecoder is configured to switch between a first memory mapping and a second memory mapping and to remap certain addresses of certain storage devices to prescribed areas of the flash memory.

Abstract: A nonvolatile semiconductor memory includes a memory block composed of a memory array having a plurality of memory cells arranged in a matrix form, each of the memory cells being composed of a nonvolatile transistor; a memory decoder necessary for erasing/writing/reading data of the nonvolatile transistor in the memory array; a charge pump necessary for erasing/writing/reading the data of the nonvolatile transistor in the memory array; a register having each of a plurality of control signals for controlling the memory decoder and the charge pump allocated to register 1 bit; and an updating device for updating a content of the register by a data processor coupled to the register. By using this updating device to update the content of the register, the memory decoder and the charge pump are controlled, the data of the memory block is erased, and data is written in/read from the nonvolatile transistor.

Abstract: A microcomputer comprises: a flash memory for storing rewriting control F/W and user S/F; a command register for specifying content of rewriting control; a address register to be subjected to rewriting-control; a data register for specifying data to be written; a power-supply pump circuit in the flash memory; and a control signal register for specifying/outputting a control signal to a memory decoder. A CPU of the microcomputer is capable of accessing these four registers to perform writing or reading. A given bit of the control signal register corresponds to a given control signal. A value written to the register becomes a control signal that will be directly supplied to both of the power supply circuit and the memory decoder, in the flash memory, to control them. By rewriting a set value of this control signal register using the rewriting control F/W according to a specified sequence, processing such as “erase” and “program” of the flash memory is performed.

Abstract: There is provided a nonvolatile semiconductor memory comprising: a memory bock composed of a memory array having a plurality of memory cells arranged in a matrix form, each of the memory cells being composed of a nonvolatile transistor; a memory decoder necessary for erasing/writing/reading data of the nonvolatile transistor in the memory array; a charge pump necessary for erasing/writing/reading the data of the nonvolatile transistor in the memory array; a register having each of a plurality of control signals for controlling the memory decoder and the charge pump allocated to register 1 bit; and means for updating a content of the register by a data processor coupled to the register. By using this updating means to update the content of the register, the memory decoder and the charge pump are controlled, the data of the memory block is erased, and data is written in/read from the nonvolatile transistor.

Abstract: Each of semiconductor chips (1) formed on a wafer (190) has a power supply voltage leading wiring (6) connected to a power supply wiring (3), a BI mode detection circuit (20) connected to the power supply voltage leading wiring (6) for detecting the supply of the power supply voltage to the power supply wiring (3), a self oscillation circuit (40) for oscillating a clock signal during the BI mode, a timing generation circuit (50) for generating and outputting a timing clock during the BI mode, a BI mode control circuit (60) for transferring control signals to circuits (70) to be performed during the BI mode, and a power source circuit (10) for supplying the power supply voltage to circuits (40, 50, 60, and 70) during the BI mode.

Abstract: Clock supply circuitry comprises a phase-locked loop or PLL frequency multiplier for generating a frequency-multiplied clock signal having a frequency that is an integral multiple of the frequency of an input clock signal. The clock supply circuitry further includes a PLL output stability detecting circuit. When the clocksupply circuitry is made to return from a clock supply stopping state in which the PLL frequency multiplier is stopping the generation of the frequency-multiplied clock signal to a clock supply state in which the PLL frequency multiplier is generating and supplying the frequency-multiplied clock signal to an internal circuit, the PLL output stability detecting circuit determines whether the frequency-multiplied clock signal from the PLL frequency multiplier becomes stable.

Abstract: A microcomputer with a built-in flash memory includes a flash controller for controlling writing/erasing of the flash memory in accordance with a command from a CPU. The flash controller produces a CPU rewriting mode designating signal and a busy signal during writing/erasing of the flash memory. In response to the two signals, awaiting mode controller implements a waiting mode by outputting a control signal to open and close an AND gate using the control signal, thereby halting a supply of a clock signal to the CPU in the waiting mode. The microcomputer can reduce the load on software for writing/erasing of the flash memory, and the load on developing software.

Abstract: Clock supply circuitry comprises a phase-locked loop or PLL frequency multiplier for generating a frequency-multiplied clock signal having a frequency that is an integral multiple of the frequency of an input clock signal. The clock supply circuitry further includes a PLL output stability detecting circuit. When the clock supply circuitry is made to return from a clock supply stopping state in which the PLL frequency multiplier is stopping the generation of the frequency-multiplied clock signal to a clock supply state in which the PLL frequency multiplier is generating and supplying the frequency-multiplied clock signal to an internal circuit, the PLL output stability detecting circuit determines whether the frequency-multiplied clock signal from the PLL frequency multiplier becomes stable.

Abstract: A microcomputer including a flash memory and a CPU for carrying out verification of data written into the flash memory. A flash controller suspends the supply of a clock signal to the CPU when it receives a verification command from the CPU, establishes a verification condition, and reads data from the flash memory. After reading the data from the flash memory, it restarts the supply of the clock signal to the CPU so that the CPU receives the data. This makes it unnecessary for a program of the CPU for writing data into the flash memory to be transferred from the flash memory to a RAM, enabling the structure of the program to be simplified.

Abstract: A semiconductor integrated circuit and a fabrication method therefor has the configuration that the number of pad driver cells 21 to 23 are equal to or more than the number of input/output control circuits 11 to 13, poly-silicon wirings 111 to 113 are connected to an input terminal IN and output terminals CP and CN in each of the input/output control circuit 11 to 13 in a wiring region LIN and poly-silicon wirings 211 to 233 are connected to input terminals CP and CN and an output terminal-IN of each of the pad driver cells 21 to 23 in the wiring region, and the poly-silicon wirings 111 to 133 are connected to poly-silicon wirings 211 to 233 through aluminum wirings.

Abstract: Power supply voltage step-down circuitry comprises a control unit for enabling either a first voltage step-down unit or a second voltage step-down unit according to a control signal applied thereto, a voltage checking unit for checking whether or not the value of a voltage generated by a power supply is equal to or greater than a predetermined value, and for furnishing a checking result signal at a predetermined level when the value of the voltage generated by the power supply is equal to or greater than a predetermined value, and a switching unit for connecting either the power supply or an output of the first step-down unit with a receiver, such as a ROM, according to whether or not the checking result signal from the voltage checking unit is at the predetermined level.

Abstract: A flash memory capable of solving a problem of a conventional flash memory in that it requires considerable time and effort to measure supply voltages generated in the flash memory during writing, erasing and verifying operations, and is difficult to acquire accurate results, because they cannot be measured by a tester and must be measured manually by putting a probe directly to voltage supply lines.

Abstract: A microcomputer capable of solving a problem in that the load of software is heavy for setting a watchdog timer in a conventional microcomputer. It includes a switching circuit which supplies a central processing unit with the output of the watchdog timer as an interrupt signal unless a memory data write mode for writing data to a memory is not designated from the outside of the microcomputer, and which inhibits an overflow signal of the watchdog timer from being supplied to the central processing unit when the memory data write mode is designated from the outside of the microcomputer.

Abstract: A microcomputer with a flash memory that solves a problem of software overload due to polling during writing or erasing of a flash memory, an interrupt caused by the completion of writing or erasing, or an interrupt caused by a monitor timer. This solution is achieved by suspending the supply of a clock signal from a clock generating circuit to a CPU, and restarting the supply of the clock signal after completion of writing or erasing. This clock signal suspension, in turn, is achieved by providing a NAND gate and an AND gate. The NAND gate NANDs a CPU rewrite mode designating signal and a write/erasure busy signal, both of which are output from a flash control circuit and are kept "1" during writing or erasing of the flash memory, thereby outputting a signal "0" during the writing or erasing. This state fixes the output of the AND gate to "0", which suspends the supply of the clock signal from the clock generator to the CPU.

Abstract: A semiconductor integrated circuit and a fabrication method therefor has the configuration that the number of pad driver cells 21 to 23 are equal to or more than the number of input/output control circuits 11 to 13, poly-silicon wirings 111 to 113 are connected to an input terminal IN and output terminals CP and CN in each of the input/output control circuit 11 to 13 in a wiring region LIN and poly-silicon wirings 211 to 233 are connected to input terminals CP and CN and an output terminal IN of each of the pad driver cells 21 to 23 in the wiring region, and the poly-silicon wirings 111 to 133 are connected to poly-silicon wirings 211 to 233 through aluminum wirings.

Abstract: A microcomputer for emulation which has been conventionally unusable when built-in RAM capacities are different, because an access to an internal function circuit is different in bus control, wait condition and the like from the access to an external memory area, and despite the above fact, which now becomes usable by including a built-in RAM 17, a higher address decoder (virtual RAM address decoder) for generating a virtual RAM address space corresponding to a plurality of virtual RAM capacities within a range in which installed capacity of the built-in RAM 17 is made a maximum value, and a RAM capacity selection flag 36 for specifying any one of a plurality of virtual RAM address spaces which can be generated by the higher address decoder 22.

Abstract: A microcomputer constituted so that an oscillation state selection signal indicative of whether a clock inputted to a first clock terminal is a clock generated at a clock generating circuit is given to a first gate circuit interposed between a first clock terminal and a second clock terminal, and a first gate circuit is placed in the transmissible state when an oscillation state selection signal is on a first state while a first gate circuit is placed in a state not to be able to transmit a signal when the oscillation state selection signal is on a second state.