Abstract: A computer system having an address space change-over circuit 8 capable of changing-over the allocation of an area of an internal ROM 22 in an address space either to an allocation in the address space most suitable for a single-chip microcomputer 20 or to an allocation in the address space more preferable for a case of connecting external memories 32, 33, and is capable of easily changing-over the address space allocation depending on whether the system operates as a single-chip microcomputer or operates as a system with external memories connected thereto.

Abstract: A microcomputer comprises control signal generation means for generating a control signal to be supplied to an external circuit having different bus cycles and outputting a plurality of control signals. Since there is no need to delay the operation speed of an external circuit which operates fast in compliance with an external circuit which operates slowly, it is possible to improve the overall operation speed.

Abstract: A microcomputer having a frequency divider for dividing, at multiple stages, the frequency of the clock generated by an oscillator circuit, a selector for selecting from among the resulting divided frequency clocks, a counter for counting the divided frequency clock selected, a switch for changing the driving ability of the oscillator circuit, and a select bit in which data on selecting the on or off control over the switch is written, wherein the driving ability of the oscillator circuit is set large in initiating oscillation and low after initiating the supply of its internal clock, independently of the program.

Abstract: A clock control circuit built in a microcomputer, wherein the supply of a system clock to peripherals that are not required to be always operated is suspended in the wait state where the supply of the system clock to a CPU is suspended, thereby decreasing a power to be consumed.

Abstract: Among a plurality of pads disposed along four sides of a semiconductor chip, complementary pads connected to individual pads by conductors are provided for the pads situated near the corners of the semiconductor chip to allow different types of packages to be used with the single semiconductor chip.

Abstract: A complementary circuit device which cancels a latch-up phenomenon to return to normal operation includes a complementary circuit, a latch-up detection circuit and a reset circuit. The complementary circuit, which is normally started from a prescribed logic state in response to an initial power application of power to the circuit, is susceptible to erroneous restart when the same is resupplied with power immediately after occurrence of a latch-up phenomenon. The latch-up detection circuit detects a latch-up phenomenon occurring in the complementary circuit. The reset circuit resets the complementary circuit to the prescribed logic state in response to an output from the latch-up detection circuit. The complementary circuit is reset again to the prescribed state in a manner similar to the case of initial application of power. The invention facilitates a normal return to operation of a complementary circuit upon cancellation of the latch-up phenomenon.

Abstract: A digital remote control apparatus for transmitting digital instruction signals to a controllable apparatus includes a transmitter for transmitting a coded digital instruction signal composed of a sequence of synchronization pulses having a predetermined period and data pulses each inserted between successive synchronization pulses at predetermined positions therein dependent upon whether the data pulses represents a "0" bit or a "1" bit. The receiving apparatus distinguishes between "0" and "1" bits by detecting the length of an interval between the leading edge of a synchronization pulse and the leading edge of an adjacent data pulse and determines the existence of noise if more than one data pulse is detected between successive synchronzation pulses.

Abstract: In a digital data transmission system, a transmitting device converts the data to be transmitted into a series of bits, in the form of data pulses. Each data pulse is positioned between successive synchronous pulses having a fixed time period, and each bit is represented by the time length between a data pulse and a preceding synchronous pulse or a succeeding synchronous pulse. The transmitting device transmits the series of the data pulses and the synchronous pulses. A receiving device receives the series of the data pulses and the synchronous pulses and decodes the same to read the data.

Abstract: A digital remote control device for use in a transmitter capable of transmitting an end code following each transmission code, which includes a counting circuit for counting the number of transmission operations performed by pressing a key or keys on the transmitter; and an end pulse changing circuit for changing a configuration of the end code such that the configuration corresponds to a count value counted by the counting circuit.