Patents by Inventor Katsunori Ueno

Katsunori Ueno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190267486
    Abstract: A vertical semiconductor device is provided, including a transistor region and a Schottky diode region, and having, in a gallium nitride layer in the Schottky diode region, a first well region, a diode trench portion that is provided in direct contact with the first well region in an array direction in which the transistor region and the Schottky diode region are arrayed, a first upper drift region that is connected to the bottom of the diode trench portion, a lower drift region that is connected to the bottom of the first well region and a bottom of the first upper drift region, and a conductive portion that is connected to an upper portion of the first upper drift region.
    Type: Application
    Filed: December 20, 2018
    Publication date: August 29, 2019
    Inventor: Katsunori UENO
  • Patent number: 10374031
    Abstract: Provided is a semiconductor device including at least two isolation trench portions; a mesa region that is provided between the at least two isolation trench portions and includes a source region having a first conduction type, a base region having a second conduction type and at least a portion thereof provided below the source region, and a gate trench portion; and a contact layer that is an epitaxial layer provided at least in contact with side portions of the mesa region and bottom portions of the isolation trench portions positioned lower than the gate trench portion, and having a second-conduction-type impurity concentration higher than that of the base region, wherein the same impurities as in the contact layer are present in the source region, or the contact layer is provided higher than the source region.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: August 6, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Katsunori Ueno, Shinya Takashima, Masaharu Edo
  • Patent number: 10366891
    Abstract: A vertical semiconductor apparatus includes: a gallium nitride substrate; a gallium nitride semiconductor layer on the gallium nitride substrate; a p-type impurity region in the gallium nitride semiconductor layer and having an element to function as an acceptor for gallium nitride; an n-type impurity region in the p-type impurity region and having an element to function as a donor for gallium nitride; and an electrode provided contacting a rear surface of the gallium nitride substrate. The element to function as the donor in the n-type impurity region includes: a first impurity element to enter sites of gallium atoms in the gallium nitride semiconductor layer; and a second impurity element different from the first impurity element and to enter sites of nitrogen atoms in the gallium nitride semiconductor layer. In the n-type impurity region, a concentration of the first impurity element is higher than that of the second impurity element.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: July 30, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Shinya Takashima, Katsunori Ueno, Masaharu Edo
  • Publication number: 20190209870
    Abstract: A radiation therapy apparatus capable of improving the accuracy of a dose distribution includes an X-ray generation device that is provided at an arm portion of a rotation gantry, a radiation detector that is insertable into the body of a patient, a dose calculation device, and a feedback control device. An X-ray generated due to collision of an electron beam with a target in the X-ray generation device is applied to an affected part (cancer) of a patient on a bed. The radiation detector which is insertable into the body detects the X-ray applied to the affected part so as to output a photon to obtain a dose rate and a dose based thereon. The feedback control device either controls the X-ray generation device such that the obtained dose becomes a set dose or controls the radiation generation device such that the obtained dose rate becomes a set dose rate.
    Type: Application
    Filed: March 3, 2017
    Publication date: July 11, 2019
    Inventors: Yuichiro UENO, Takahiro TADOKORO, Yasushi NAGUMO, Katsunori UENO, Kouichi OKADA, Shuichi HATAKEYAMA
  • Publication number: 20190204457
    Abstract: Provided is a radiation monitor, including: a radiation detection unit which includes a radiation detection element, the radiation detection element emitting light of a predetermined light emission wavelength; a light emission unit which emits light of a wavelength different from the light emission wavelength; a wavelength selection unit which passes the light of the light emission wavelength, and is set to a first mode to block the light from the light emission unit; an optical transmission line which transmits the light; a light detection unit which converts the light passing through the wavelength selection unit into an electric pulse; and a control unit which measures a count rate of the electric pulse, and determines whether at least the light emission unit is degraded on the basis of the count rate and a light intensity of the light emission unit.
    Type: Application
    Filed: August 8, 2017
    Publication date: July 4, 2019
    Inventors: Takahiro TADOKORO, Katsunori UENO, Yuichiro UENO, Kouichi OKADA, Shuichi HATAKEYAMA, Yasushi NAGUMO, Yoshinobu SAKAKIBARA, Toru SHIBUTANI, Takahiro ITOU
  • Publication number: 20190175950
    Abstract: The radiation detection device includes a plurality of radiation detectors arranged in a row and is inserted into the body of patient subjected to the X-ray therapy. An X-ray detection signal (photon) is output from each of the radiation detectors that detects the X-ray applied to the patient. The dose rate measurement device separately connected to each of the radiation detectors obtains the dos rate at the position of each radiation detector based on the signals. The irradiation direction determination device determines whether the row of radiation detectors matches the irradiation direction of the X-ray using the dos rate obtained by each of the dose rate measurement devices. When the row of radiation detectors matches the irradiation direction, the energy distribution analysis device obtains an energy distribution using the dose rate at the positions of the radiation detectors by applying, for example, an inverse problem analysis called an unfolding method.
    Type: Application
    Filed: June 28, 2016
    Publication date: June 13, 2019
    Inventors: Yasushi NAGUMO, Takahiro TADOKORO, Yuichiro UENO, Katsunori UENO, Kouichi OKADA, Shuichi HATAKEYAMA
  • Publication number: 20190165187
    Abstract: A diode is provided, the diode including: a semiconductor layer of a first conductivity type, configured to have a trench structure and be an epitaxial layer of a wide gap semiconductor; a semiconductor layer of a second conductivity type, configured to be at least in contact with a side wall of the trench structure and be an epitaxial layer of the wide gap semiconductor; and an electrode configured to be in contact with the semiconductor layer of the first conductivity type and the semiconductor layer of the second conductivity type, on the semiconductor layer of the first conductivity type and the semiconductor layer of the second conductivity type.
    Type: Application
    Filed: October 30, 2018
    Publication date: May 30, 2019
    Inventors: Ryo TANAKA, Shinya TAKASHIMA, Katsunori UENO, Masaharu EDO
  • Publication number: 20190157448
    Abstract: A manufacturing method of a vertical GaN-based semiconductor device having: a GaN-based semiconductor substrate; a GaN-based semiconductor layer including a drift region having doping concentration of an n type impurity, which is lower than that of the GaN-based semiconductor substrate, and is provided on the GaN-based semiconductor substrate; and MIS structure having the GaN-based semiconductor layer, an insulating film contacting the GaN-based semiconductor layer, and a conductive portion contacting the insulating film, the method includes: implanting an n type dopant in a back surface of the GaN-based semiconductor substrate after forming of the MIS structure, and annealing the GaN-based semiconductor substrate after the implanting of the n type dopant.
    Type: Application
    Filed: November 1, 2018
    Publication date: May 23, 2019
    Inventors: Shinya TAKASHIMA, Katsunori UENO, Masaharu EDO
  • Publication number: 20190131409
    Abstract: Provided is a manufacturing method of a semiconductor device including a vertical MOSFET having a planar gate. The manufacturing method of a semiconductor device includes forming a n-type gallium nitride layer on a gallium nitride monocrystalline substrate, and forming an impurity-implanted region that contains impurities at a uniform concentration in a direction parallel to a main surface of the gallium nitride monocrystalline substrate, by ion-implanting the impurities into the n-type gallium nitride layer, where the impurities include at least one type selected from among magnesium, beryllium, calcium and zinc. Here, at least part of the impurity-implanted region serves as a channel forming region of the vertical MOSFET.
    Type: Application
    Filed: December 26, 2018
    Publication date: May 2, 2019
    Inventors: Katsunori UENO, Shinya TAKASHIMA
  • Publication number: 20190115215
    Abstract: A vertical semiconductor apparatus includes: a gallium nitride substrate; a gallium nitride semiconductor layer on the gallium nitride substrate; a p-type impurity region in the gallium nitride semiconductor layer and having an element to function as an acceptor for gallium nitride; an n-type impurity region in the p-type impurity region and having an element to function as a donor for gallium nitride; and an electrode provided contacting a rear surface of the gallium nitride substrate. The element to function as the donor in the n-type impurity region includes: a first impurity element to enter sites of gallium atoms in the gallium nitride semiconductor layer; and a second impurity element different from the first impurity element and to enter sites of nitrogen atoms in the gallium nitride semiconductor layer. In the n-type impurity region, a concentration of the first impurity element is higher than that of the second impurity element.
    Type: Application
    Filed: March 27, 2018
    Publication date: April 18, 2019
    Inventors: Shinya TAKASHIMA, Katsunori UENO, Masaharu EDO
  • Patent number: 10256292
    Abstract: In order to improve the dynamic characteristics of a vertical MOSFET using GaN, it is an objective of the present invention to reduce the resistance of a current path with a long hole movement distance in a p-type well. Provided is a vertical MOSFET including a gallium nitride layer having a main surface that is a non-polar surface; a p-type well region that is provided with a stripe shape in the main surface of the gallium nitride layer; and a stripe-shaped electrode provided above the p-type well region. Hole mobility is higher in a direction orthogonal to an extension direction of the stripe-shaped electrode than in the extension direction, among directions in a plane parallel to the main surface.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: April 9, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Shinya Takashima, Katsunori Ueno, Masaharu Edo
  • Patent number: 10224122
    Abstract: An object of the invention is to provide a reactor instrumentation system that can be easily repaired or replaced. The invention includes: an instrumentation tube provided in a reactor core; a gas flow pipe provided in the instrumentation tube; a suction mechanism for supplying gas containing oxygen to the gas flow pipe; and a nuclide analysis device for measuring a nuclide in the gas in the gas flow pipe. According to the invention, it is possible to provide a reactor instrumentation system that can be easily repaired or replaced.
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: March 5, 2019
    Assignee: Hitachi, Ltd.
    Inventors: Kouichi Okada, Takahiro Tadokoro, Katsunori Ueno, Yasushi Nagumo
  • Patent number: 10181514
    Abstract: In a case where a semiconductor layer is epitaxially grown on a step shape formed due to CBL (current blocking layer) formation, the crystallinity of the semiconductor layer lowers. Also, a GaN layer that is epitaxially regrown on the CBL is not formed continuously by epitaxial growth, and therefore the crystallinity of the GaN layer lowers. A vertical semiconductor device manufacturing method is provided that comprises: a step of epitaxially growing a gallium nitride-based n-type semiconductor layer on a gallium nitride-based semiconductor substrate; a step of epitaxially growing a gallium nitride-based p-type semiconductor layer on the n-type semiconductor layer; and a step of ion-implanting p-type impurities to form a p+-type embedded region selectively in a predetermined depth range across the boundary between the n-type semiconductor layer and the p-type semiconductor layer.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: January 15, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Hideaki Matsuyama, Shinya Takashima, Katsunori Ueno, Takuro Inamoto, Masaharu Edo
  • Patent number: 10176981
    Abstract: If a SiO2 film is formed on a semiconductor substrate using TEOS (tetraethylorthosilicate: Si(OC2H5)4), carbon (C) may be mixed in the SiO2 film in some cases. In a SiO2 film, carbon may function as fixed charges. For example, if carbon (C) is mixed in a SiO2 film as a gate insulating film of a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), the gate threshold voltage (Vth) may fluctuate. A semiconductor device using a gallium nitride semiconductor layer is provided. The semiconductor device includes: a silicon dioxide film that is provided at least partially in direct contact with the gallium nitride semiconductor layer and has impurity atoms, wherein the silicon dioxide film contains as the impurity atoms: carbon at concentration higher than 0 cm?3 and lower than 2E+18 cm?3; and gallium at concentration equal to or lower than 1E+17 cm?3.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: January 8, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Katsunori Ueno, Kiyokazu Nakagawa
  • Publication number: 20190006184
    Abstract: A gallium nitride based semiconductor device is provided, where when a thickness of a transition layer is defined as the followings, the thickness of the transition layer is less than 1.5 nm: (i) a distance between a depth position at which an atomic composition of nitrogen element constituting the gallium nitride based semiconductor layer is ½ relative to that at a position on the GaN based semiconductor layer side sufficiently away from the transition layer, and a depth position at which an atomic composition of a metal element is ½ of a value of a maximum if an atomic composition of the metal element constituting an insulating layer has the maximum, or a depth position at which an atomic composition of the metal element is ½ relative to that at a position on the insulating layer side sufficiently away from the transition layer if not having the maximum.
    Type: Application
    Filed: June 28, 2018
    Publication date: January 3, 2019
    Inventors: Hideaki MATSUYAMA, Shinya TAKASHIMA, Katsunori UENO, Ryo TANAKA, Masaharu EDO, Daisuke MORI, Hirotaka SUDA, Hideaki TERANISHI, Chizuru INOUE
  • Patent number: 10170564
    Abstract: Provided is a manufacturing method of a semiconductor device including a vertical MOSFET having a planar gate. The manufacturing method of a semiconductor device includes forming a n-type gallium nitride layer on a gallium nitride monocrystalline substrate, and forming an impurity-implanted region that contains impurities at a uniform concentration in a direction parallel to a main surface of the gallium nitride monocrystalline substrate, by ion-implanting the impurities into the n-type gallium nitride layer, where the impurities include at least one type selected from among magnesium, beryllium, calcium and zinc. Here, at least part of the impurity-implanted region serves as a channel forming region of the vertical MOSFET.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: January 1, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Katsunori Ueno, Shinya Takashima
  • Patent number: 10141192
    Abstract: When a nitride semiconductor layer into which impurity ions have been implanted is subjected to annealing after a protective film is provided on the nitride semiconductor layer, vacancy defects may be disadvantageously prevented from escaping outside through the surface of the nitride semiconductor layer and disappearing. A manufacturing method of a semiconductor device including a nitride semiconductor layer is provided. The manufacturing method includes implanting impurities into the nitride semiconductor layer, performing a first annealing on the nitride semiconductor layer at a first temperature within an atmosphere of a nitrogen atom containing gas without providing a protective film on the nitride semiconductor layer, forming the protective film on the nitride semiconductor layer after the first annealing, and after the protective film is formed, performing a second annealing on the nitride semiconductor layer at a second temperature that is higher than the first temperature.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: November 27, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Shinya Takashima, Katsunori Ueno, Masaharu Edo
  • Patent number: 10128106
    Abstract: When a defect region is present near the pn junction in a GaN layer, lattice defects are present in the depletion layer. Therefore, when a reverse bias is applied to the pn junction, the defects in the depletion layer cause the generated current to flow as a leakage current. The leakage current flowing through the depletion layer can cause a decrease in the withstand voltage at the pn junction. Provided is a semiconductor device using gallium nitride, including a gallium nitride layer including an n-type region. The gallium nitride layer includes a first p-type well region and a second p-type well region that is provided on at least a portion of the first p-type well region and has a peak region with a higher p-type impurity concentration than the first p-type well region.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: November 13, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Shinya Takashima, Katsunori Ueno, Masaharu Edo
  • Patent number: 10121876
    Abstract: In case of performing annealing at a temperature of 1300° C. or higher, it is not possible to sufficiently suppress escape of nitrogen from a GaN layer even if a cap layer is provided thereon. Thereby, the front surface of the GaN layer is roughened. A semiconductor device manufacturing method of manufacturing a semiconductor device having a nitride semiconductor layer is provided. The semiconductor device manufacturing method includes: implanting, into a predetermined region of the nitride semiconductor layer, n-type or p-type impurities relative to the nitride semiconductor layer; forming, by atomic layer deposition, a first protective film containing a nitride on and in direct contact with at least the predetermined region; and annealing the nitride semiconductor layer and the first protective film at a temperature of 1300° C. or higher.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: November 6, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Shinya Takashima, Katsunori Ueno, Masaharu Edo
  • Patent number: 10069003
    Abstract: When a channel formation region is formed of GaN in a MOSFET, there are cases where the actual threshold voltage (Vth) is lower than the setting value thereof and the actual carrier mobility (?) during the ON state is lower than the setting value thereof. The reason for threshold voltage (Vth) and the carrier mobility (?) being lower than the setting values is unknown. A MOSFET including a gallium nitride substrate, an epitaxial layer made of gallium nitride provided on top of the gallium nitride substrate, a gate insulating film provided in direct contact with the epitaxial layer, and a gate electrode provided in contact with the gate insulating film. The gallium nitride substrate has a dislocation density less than or equal to 1E+6 cm?2, and the epitaxial layer has a region with a p-type impurity concentration less than or equal to 5E+17 cm?3.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: September 4, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Katsunori Ueno