Patents by Inventor Katsuo Oshima

Katsuo Oshima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100304311
    Abstract: A method of producing a resist pattern includes the steps of: forming a resist layer on the semiconductor substrate; performing a first exposure process on the resist layer; performing a first developing process for developing the resist layer to form a first resist pattern having an excess region; performing a first cleaning process; performing a second exposure process on the first resist pattern; performing a second developing process on the first resist pattern to remove the excess region from the first resist pattern so that a second resist pattern corresponding to the specific resist pattern is formed; and performing a second cleaning process.
    Type: Application
    Filed: May 25, 2010
    Publication date: December 2, 2010
    Inventors: Katsuo OSHIMA, Tokio Shino
  • Patent number: 7629223
    Abstract: A method for manufacturing a semiconductor device includes forming a plurality of trenches for element isolation and a plurality of trenches for alignment mark on a substrate. The substrate has an active region. The method also includes laminating an oxide film on the substrate and over both of the trenches. The method also includes etching the oxide film using a resist mask that masks the element isolation trenches, so that the oxide film laminated in the active region and the oxide film laminated in the alignment mark trenches are removed. The method also includes polishing a surface of the substrate to planarize or smooth the surface of the substrate. Accordingly, those portions of the oxide film which project from the substrate surface are eliminated and the oxide film remains only inside the element isolation trenches. This divides the active region into a plurality of individual active regions for the respective semiconductor elements.
    Type: Grant
    Filed: November 20, 2008
    Date of Patent: December 8, 2009
    Assignee: Oki Semiconductor Co., Ltd.
    Inventors: Tadashi Narita, Katsuo Oshima
  • Publication number: 20090137092
    Abstract: A method for manufacturing a semiconductor device includes forming a plurality of trenches for element isolation and a plurality of trenches for alignment mark on a substrate. The substrate has an active region. The method also includes laminating an oxide film on the substrate and over both of the trenches. The method also includes etching the oxide film using a resist mask that masks the element isolation trenches, so that the oxide film laminated in the active region and the oxide film laminated in the alignment mark trenches are removed. The method also includes polishing a surface of the substrate to planarize or smooth the surface of the substrate. Accordingly, those portions of the oxide film which project from the substrate surface are eliminated and the oxide film remains only inside the element isolation trenches. This divides the active region into a plurality of individual active regions for the respective semiconductor elements.
    Type: Application
    Filed: November 20, 2008
    Publication date: May 28, 2009
    Applicant: OKI SEMICONDUCTOR CO., LTD.
    Inventors: Tadashi Narita, Katsuo Oshima
  • Patent number: 6869738
    Abstract: The main mask pattern of a photomask is corrected by adding serifs of one type (inner or outer) to a pair of mutually adjacent corners in the pattern, and adding a serif of the opposite type (outer or inner) to the edge between the corners. When the photomask is used to create a resist pattern by photolithography in the fabrication of a semiconductor device, the serifs combine to produce an optical proximity correction that reduces corner rounding and increases edge straightness in the resist pattern.
    Type: Grant
    Filed: November 27, 2002
    Date of Patent: March 22, 2005
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Katsuo Oshima, Koki Muto
  • Patent number: 6838643
    Abstract: An apparatus for baking a semiconductor wafer having a resist pattern thereon includes a baking oven in which the semiconductor wafer is placed and heated, and a first hot plate which is provided in the baking oven to heat an entire bottom surface of the semiconductor wafer. The apparatus also includes a gas supply unit having a gas introducing path, through which the purge gas is introduced into the baking oven, and a gas exhaust path, through which the purge gas is exhausted out of the baking oven. A gas temperature controller controls a temperature of the purge gas in order that the purge gas flowing around a peripheral edge or outer portion of the wafer has a higher temperature than that around the center or inner portion of the wafer.
    Type: Grant
    Filed: July 18, 2002
    Date of Patent: January 4, 2005
    Assignee: OKI Electric Industry Co., Ltd.
    Inventors: Shouzou Kobayashi, Takamitsu Furukawa, Keisuke Tanaka, Kouhei Shimoyama, Akira Watanabe, Tadashi Nishimuro, Koki Muto, Azusa Yanagisawa, Katsuo Oshima
  • Publication number: 20030162103
    Abstract: The main mask pattern of a photomask is corrected by adding serifs of one type (inner or outer) to a pair of mutually adjacent corners in the pattern, and adding a serif of the opposite type (outer or inner) to the edge between the corners. When the photomask is used to create a resist pattern by photolithography in the fabrication of a semiconductor device, the serifs combine to produce an optical proximity correction that reduces corner rounding and increases edge straightness in the resist pattern.
    Type: Application
    Filed: November 27, 2002
    Publication date: August 28, 2003
    Inventors: Katsuo Oshima, Koki Muto
  • Publication number: 20030057198
    Abstract: An apparatus for baking a semiconductor wafer having a resist pattern thereon, comprising: a baking oven in which the semiconductor wafer is placed and heated; a first hot plate which is provided in the baking oven to heat an entire bottom surface of the semiconductor wafer; a gas supply unit which comprises a gas introducing path, through which the purge gas is introduced into the baking oven, and a gas exhaust path, through which the purge gas is exhausted out of the baking oven; and a gas temperature controller which controls a temperature of the purge gas in order that the purge gas flowing around a peripheral edge or outer portion of the wafer has a higher temperature than that around the center or inner portion of the wafer.
    Type: Application
    Filed: July 18, 2002
    Publication date: March 27, 2003
    Inventors: Shouzou Kobayashi, Takamitsu Furukawa, Keisuke Tanaka, Kouhei Shimoyama, Akira Watanabe, Tadashi Nishimuro, Koki Muto, Azusa Yanagisawa, Katsuo Oshima
  • Patent number: 6455438
    Abstract: According to the present invention, a semiconductor device is fabricated by the following processes. First, a film to be etched is formed on a semiconductor substrate. On the film to be etched is formed a resist film. Then, a first pattern group including first patterns having a first size and a second pattern group including second patterns arranged outside of the first pattern group are formed by exposure. The resist film is then developed to form openings in the resist film so that the resultant openings correspond to the first and second patterns, respectively. The openings are then made smaller by annealing the resist film. The aforementioned processes enables openings having substantially the same shape to be formed in the film to be etched.
    Type: Grant
    Filed: September 15, 2000
    Date of Patent: September 24, 2002
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Azusa Yanagisawa, Koki Muto, Tadashi Nishimuro, Katsuo Oshima, Akira Watanabe, Akihiko Nara, Kouhei Shimoyama, Keisuke Tanaka, Takamitsu Furukawa, Shouzou Kobayashi