Method and apparatus for performing baking treatment to semiconductor wafer
An apparatus for baking a semiconductor wafer having a resist pattern thereon includes a baking oven in which the semiconductor wafer is placed and heated, and a first hot plate which is provided in the baking oven to heat an entire bottom surface of the semiconductor wafer. The apparatus also includes a gas supply unit having a gas introducing path, through which the purge gas is introduced into the baking oven, and a gas exhaust path, through which the purge gas is exhausted out of the baking oven. A gas temperature controller controls a temperature of the purge gas in order that the purge gas flowing around a peripheral edge or outer portion of the wafer has a higher temperature than that around the center or inner portion of the wafer.
Latest Trimeris, Inc. Patents:
- HIV fusion inhibitor peptides with improved biological properties
- Isolated peptides derived from human immunodeficiency virus types 1 and 2 containing fusion inhibitory domains
- Antiviral peptide-polymer conjugate comprising a polymer covalently attached to two or more synthetic HIV gp41 HR1 and/or HR2 peptides
- Methods for inhibition of membrane-fusion-associated events, including Hepatitis B virus transmission
- HIV fusion inhibitor peptides with improved biological properties
This application claims the priority of Application No. 2001-290970, filed Sep. 25, 2001 in Japan, the subject matter of which is incorporated herein by reference.
TECHNICAL FIELD OF THE INVENTIONThis invention relates to method and apparatus for performing baking treatment to a semiconductor wafer.
BACKGROUND OF THE INVENTIONA baking process is carried out as one of photolithographic processes, used for fabricating semiconductor integrated circuits. In a baking process, a semiconductor wafer is baked by using a baking oven.
A resist layer formed on a semiconductor is exposed with KrF light and developed to form a pre-designed resist pattern. After that, a high-temperature baking treatment is carried out on the wafer. A hot-plate type of baking oven has been used. The bottom surface of a wafer, which is arranged in the oven, is heated by a hot plate, while a purge gas is supplied into the oven. During such a process, the resist pattern is shunk. A resist pattern having a width narrower than 0.10 μm can be formed.
According to the above-described baking process, a change rate of size of a resist pattern is does not occur equally on the entire surface of the wafer. That is, the resist pattern is more narrowed at the center or inner portion of the wafer than around the peripheral edge or outer portion of the wafer. As a result, ICs or LSIs formed on the wafer may have different quality.
OBJECTS OF THE INVENTIONAccordingly, an object of the present invention is to provide a method for baking a semiconductor wafer, in which a resist pattern is changed in size at a uniform rate on the wafer entirely.
Another object of the present invention is to provide a baking apparatus, in which a resist pattern can be baked with a change of size occurring at a uniform rate over the entire wafer.
Additional objects, advantages and novel features of the present invention will be set forth in part in the description that follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
SUMMARY OF THE INVENTIONAccording to a first aspect of the present invention, an apparatus for baking a semiconductor wafer having a resist pattern thereon, includes: a baking oven in which the semiconductor wafer is placed and heated; a first hot plate which is provided in the baking oven to heat an entire bottom surface of the semiconductor wafer; a gas supply unit which comprises a gas introducing path, through which the purge gas is introduced into the baking oven, and a gas exhaust path, through which the purge gas is exhausted out of the baking oven; and a gas temperature controller which controls a temperature of the purge gas in order that the purge gas flowing around a peripheral edge or outer portion of the wafer has a higher temperature than that around the center or inner portion of the wafer.
According to a second aspect of the present invention, an apparatus for baking a semiconductor wafer having a resist pattern thereon, includes: a baking oven in which the semiconductor wafer is placed and heated; a first hot plate which is provided in the baking oven to heat an entire bottom surface of the semiconductor wafer; a gas supply unit which comprises a gas introducing path, through which the purge gas is introduced into the baking oven, and a gas exhaust path, through which the purge gas is exhausted out of the baking oven; and a plate temperature controller which controls a temperature of the first hot plate in order that the first hot plate has a higher temperature at peripheral edge of the semiconductor wafer than that around the center of the semiconductor wafer.
According to a third aspect of the present invention, a method for baking a semiconductor wafer having a resist pattern thereon, includes the steps of: setting the semiconductor wafer in a baking oven; heating an entire bottom surface of the semiconductor wafer using a first hot plate; supplying a purge gas onto an upper surface of the semiconductor wafer; and controlling a temperature of the purge gas in order that the purge gas flowing around a peripheral edge of the semiconductor wafer has a higher temperature than that flowing around the center of the wafer.
According to a fourth aspect of the present invention, a method for baking a semiconductor wafer having a resist pattern thereon, includes the steps of: setting the semiconductor wafer in a baking oven; heating an entire bottom surface of the semiconductor wafer using a first hot plate; supplying a purge gas onto an upper surface of the semiconductor wafer; and controlling a temperature of the first hot plate in order that first hot plate has a higher temperature at peripheral edge of the semiconductor wafer than that around the center of the semiconductor wafer.
In the following detailed description of the preferred embodiments, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific preferred embodiments in which the inventions may be practiced. These preferred embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other preferred embodiments may be utilized and that logical, mechanical and electrical changes may be made without departing from the spirit and scope of the present inventions. The following detailed description is, therefore, not to be taken in a limiting sense, and scope of the present inventions is defined only by the appended claims.
First Preferred Embodiment
As shown in
As shown in
As shown in
As shown in
In
The apparatus 1 may include a plurality of temperature sensors 23. If so, the temperature controller 24, for example, operates in accordance with the average value of sensing results of the plural sensors 23.
A resist pattern is formed using the above-described apparatus 1 as follows: First, a resist is coated on a semiconductor wafer 10, then the resist layer is exposed by a circuit pattern (for example, using KrF light). After that, the circuit pattern is developed to form a resist pattern. The semiconductor wafer 10 having such a formed resist pattern on it is introduced into the baking oven 11 from the wafer-introducing opening 14. The semiconductor wafer 10 is put on the wafer holder 25. Next, the inner-wall ring 15 is raised up to close the wafer-introducing opening 14 to form air-tightness in the baking oven 11. After that, a baking treatment is carried out on the semiconductor wafer 10 in the baking oven 11.
In a baking treatment, the semiconductor wafer 10 is heated by the heater 22 provided in the hot plate 21. The hot plate 21 and heater 22 are shaped and made of a material so as to heat an entire lower surface of the semiconductor wafer 10 uniformly. While the semiconductor wafer 10 is heated by the hot plate 21, a purge gas (for example, N2 gas) is introduced through the gas-introducing paths 16 into the baking oven 11. The purge gas flows radially from an area adjacent the peripheral edge of the semiconductor wafer 10 toward an area adjacent the center of the wafer 10, and is exhausted through the gas-exhaust paths 19. The purge gas is heated by the heaters 17 in the gas-introducing paths 16 to have a temperature that is higher than that of the hot plate 21.
The optimum temperatures of the hot plate 21 and purge gas are determined based on measured data of the resist pattern after its baking treatment. That is because the optimum temperatures vary in response to many factors, including a shape and a size of the baking oven 11; a material and widths of the resist pattern on the wafer 10; a degree of heat-flow; the numbers, diameters, positions of the gas-introducing paths 16 and gas-exhaust paths 19; and a composition, a flow rate, and a flowing route of the purge gas. A voltage to be applied to the heaters 17 arranged in the gas-introducing paths 16 can be controlled in accordance with an output of the temperature sensor 23 or other sensors, which may be arranged adjacent the gas-introducing paths 16.
According to the apparatus 1, the gas-introducing paths 16 are arranged at regions adjacent the peripheral edge of the semiconductor wafer 10 in the lower cover 12; and the gas-exhaust paths 19 are arranged at regions adjacent the center of the semiconductor wafer 10 in the upper cover. Therefore, the purge gas is mainly flowing radially as shown by arrows in
The temperature of the purge gas, which is heated before being introduced into the baking oven 11, is decreased gradually above the semiconductor wafer 10, and then is exhausted through the gas-exhaust paths 19. The temperature of the purge gas is higher at a region adjacent the peripheral edge of the semiconductor wafer in which the purge gas enters the baking oven 11 than at a region adjacent the center of the semiconductor wafer 10 where it exits the baking oven 11. The distribution or ranging of the temperature of the purge gas is gradual. As a result, the resist pattern formed at a region adjacent the peripheral edge of the wafer 10 may be changed in size (shrunken) more remarkably as compared to that by a conventional method. In other words, the resist pattern is changed in size at a uniform rate over the entire semiconductor wafer 10. Preferably, the outer region of the semiconductor wafer 10 has a temperature 1-2° higher than the inner region.
When the baking treatment is completed, the valves 18 and 20 are closed and the inner-wall ring 15 is moved to its lower position. After that, the semiconductor wafer 10 is taken out from the wafer-introducing opening 14.
As described above, according to the first preferred embodiment, while the semiconductor wafer 10 is heated entirely by the hot plate 21, the purge gas is heated by the heater 17 and is applied onto the upper surface of the semiconductor wafer 10. The gas-introducing paths 16 and gas-exhaust paths 19 are arranged at regions adjacent the peripheral edge and the center of the semiconductor wafer 10, respectively. The temperature of the semiconductor wafer 10 is higher around the peripheral edge than around the center thereof. As a result, the change rate of size of a resist pattern is made equally on the entire surface of the wafer 10; and therefore, ICs or LSIs formed on the wafer 10 can be fabricated with a higher reliability.
Second Preferred Embodiment
As shown in
As shown in
As shown in
As shown in
In a baking treatment, the semiconductor wafer 10 is heated by the heater 22 provided in the hot plate 21. The hot plate 21 and heater 22 are shaped and made of a material so as to heat an entire lower surface of the semiconductor wafer 10 uniformly. While the semiconductor wafer 10 is heated by the hot plate 21, a purge gas (for example, N2 gas) is introduced through the gas-introducing path 36 into the baking oven 31. The purge gas flows radially from an area adjacent the center of the wafer 10 toward an area adjacent the peripheral edge of the semiconductor wafer 10, and is exhausted through the gas-exhaust paths 39. The purge gas is in contact with a cooling pipe 37a and is cooled in the gas-introducing path 36 to have a temperature, that is lower than that of the hot plate 21.
The optimum temperatures of the hot plate 21 and purge gas are determined based on measured data of the resist pattern after its baking treatment. That is because the optimum temperatures vary in response to many factors, including a shape and a size of the baking oven 31; a material and widths of the resist pattern on the wafer 10; a degree of heat-flow; the numbers, diameters, positions of the gas-introducing path 36 and gas-exhaust paths 39; and a composition, a flow rate, and a flowing route of the purge gas. The chiller 37 arranged at the gas-introducing path 36 can be controlled in accordance with an output of the temperature sensor 23 at the center of the hot plate 21, or other sensors, which may be arranged adjacent the gas-introducing path 36.
According to the apparatus 2, the gas-introducing path 36 is arranged at a region adjacent the center of the semiconductor wafer 10 in the upper cover 33; and the gas-exhaust paths 39 are arranged at regions adjacent the peripheral edge of the semiconductor wafer 10 in the lower cover 32. Therefore, the purge gas is mainly flowing radially as shown by arrows in
The temperature of the purge gas, which is cooled before being introduced into the baking oven 31, is increased gradually above the semiconductor wafer 10, and then is exhausted through the gas-exhaust paths 39. The temperature of the purge gas is higher at a region adjacent the peripheral edge of the semiconductor wafer in which the purge gas exits the baking oven than at a region adjacent the center of the semiconductor wafer 10 in which the purge gas enters the baking oven. The distribution or ranging of the temperature of the purge gas is gradual. As a result, the resist pattern formed at a region adjacent the peripheral edge of the wafer 10 may be changed in size (shrunken) more remarkably as compared to that by a conventional method. In other words, the resist pattern is changed in size at a uniform rate on the semiconductor wafer 10 entirely. Preferably, the outer region of the semiconductor wafer 10 has a temperature 1-2° higher than the inner region.
When the baking treatment is completed, the valves 38 and 40 are closed and the inner-wall ring 35 is moved to its lower position. After that, the semiconductor wafer 10 is taken out from the wafer-introducing opening 14.
As described above, according to the second preferred embodiment, while the semiconductor wafer 10 is heated entirely by the hot plate 21, the purge gas is cooled by the chiller 17 and is applied onto the upper surface of the semiconductor wafer 10. The gas-introducing paths 36 and gas-exhaust paths 39 are arranged at regions adjacent the center and the peripheral edge of the semiconductor wafer 10, respectively. The temperature of the semiconductor wafer 10 is higher at around the peripheral edge than around the center thereof. As a result, a change rate of size of a resist pattern is made the same on the entire surface of the wafer 10; and therefore, ICs or LSIs formed on the wafer 10 can be fabricated with a higher reliability.
Third Preferred Embodiment
The apparatus 3 includes a flow-control board 42 which is used to control a flow direction of a purge gas in a baking oven 41. The flow-control board 42 is arranged above a semiconductor wafer 10 in the baking oven 41. The apparatus 3 also includes a lift mechanism 43 which rises and falls the flow-control board 42. The flow-control board 42 is provided at its center with an opening 44, through which a purge gas is passing onto the semiconductor wafer 10.
As shown in
As shown in
As shown in
As shown in
In a baking treatment, the semiconductor wafer 10 is set at the wafer holder 25 in the baking oven 41 then, the inner-wall ring 35 goes up and closes the baking oven 41. Next, the flow-control board 42 comes down toward the semiconductor wafer 10, as shown in FIG. 9. The semiconductor wafer 10 is heated by the heater 22 provided in the hot plate 21. The hot plate 21 and heater 22 are shaped and made of a material so as to heat an entire lower surface of the semiconductor wafer 10 uniformly.
While the semiconductor wafer 10 is heated by the hot plate 21, a purge gas (for example, N2 gas) is introduced through the gas-introducing path 36 and the opening 44 of the flow-control board 42 into the baking oven 41. The purge gas is flowing radially from an area adjacent the center of the wafer 10 toward an area adjacent the peripheral edge of the semiconductor wafer 10, and is exhausted through the gas-exhaust paths 39. The purge gas is in contact with a cooling pipe 37a and is cooled in the gas-introducing path 36 to have a temperature, which is lower than that of the hot plate 21.
The optimum temperatures of the hot plate 21 and purge gas are determined based on measured data of the resist pattern after its baking treatment. That is because the optimum temperatures vary in response to many factors, including a shape and a size of the baking oven 41; a material and widths of the resist pattern on the wafer 10; a degree of heat-flow; the numbers, diameters, positions of the gas-introducing path 36 and gas-exhaust paths 39; and a composition, a flow rate, a flowing route of the purge gas. The chiller 37 arranged at the gas-introducing path 36 can be controlled in accordance with an output of the temperature sensor 23 or other sensors, which may be arranged adjacent the gas-introducing path 36.
According to the apparatus 3, the gas-introducing path 36 and opening 44 of the flow-control board 42 are arranged directly above the center of the semiconductor wafer 10; and the gas-exhaust paths 39 are arranged at regions adjacent the peripheral edge of the semiconductor wafer 10 in the lower cover 32. Therefore, the purge gas is mainly flowing radially as shown by arrows in
The temperature of the purge gas, which is cooled before being introduced into the baking oven 41, is increased gradually above the semiconductor wafer 10, and then is exhausted through the gas-exhaust paths 39. The temperature of the purge gas is higher at a region adjacent the peripheral edge of the semiconductor wafer in which the purge gas than at a region adjacent the center of the semiconductor wafer 10. The distribution or ranging of the temperature of the purge gas is gradual. As a result, the resist pattern formed at a region adjacent the peripheral edge of the wafer 10 may be changed in size (shrunken) more remarkably as compared to that by a conventional method. In other words, the resist pattern is changed in size at a uniform rate on the semiconductor wafer 10 entirely. Preferably, the outer region of the semiconductor wafer 10 has a temperature 1-2° C. higher than the inner region.
When the baking treatment is completed, the valves 38 and 40 are closed and the inner-wall ring 35 is moved to its lower position. After that, the semiconductor wafer 10 is taken out from the wafer-introducing opening 14.
As described above, according to the third preferred embodiment, while the semiconductor wafer 10 is heated entirely by the hot plate 21, the purge gas is cooled by the chiller 17 and is applied onto the upper surface of the semiconductor wafer 10. The gas-introducing paths 36 and gas-exhaust paths 39 are arranged at regions adjacent the center and the peripheral edge of the semiconductor wafer 10, respectively. The temperature of the semiconductor wafer 10 is higher at around the peripheral edge than around the center thereof. As a result, change rate of size of a resist pattern is made equally on the entire surface of the wafer 10; and therefore, ICs or LSIs formed on the wafer 10 can be fabricated with a higher reliability. As compared to the second preferred embodiment, a flow direction of the purge gas can be controlled precisely using the flow control board 42 with the center opening 44.
The flow-control board 42 and lift mechanism 43 are applicable to the apparatus 1 according to the first preferred embodiment.
Fourth Preferred Embodiment
The apparatus 4 includes a flow-control board 52, which is used to control a flow direction of a purge gas in a baking oven 51; a lift mechanism 53 which rises and falls the flow-control board 52; and a temperature sensor 56 which detects a temperature at an upper surface of the semiconductor wafer 10. The flow-control board 52 is arranged above a semiconductor wafer 10 in the baking oven 51. The flow-control board 52 is provided at its center with an opening 44, through which a purge gas is passing onto the semiconductor wafer 10, and with a shutter 55.
The shutter 55 is arranged at the opening 54 of the flow-control board 52 to adjust an aperture size of the opening 54. The shutter 55 is controlled in accordance with a detection result of the sensor 56. For example, the aperture formed by the shutter 55 is controlled to be wider when the temperature at the upper surface of the semiconductor wafer 10 is detected to be high. The shutter 55 may be controlled in accordance with a material or composition of the resist pattern formed on the wafer 10. A shrink rate of a resist pattern may vary according to its composition and/or quality.
As shown in
The shape of the flow-control board 52; the shape position and number of the opening 54; the structure of the shutter 55; and the number of the sensor 56 are not limited by this embodiment.
As shown in
As shown in
As shown in
In a baking treatment, the semiconductor wafer 10 is set at the wafer holder 25 in the baking oven 51 then, the inner-wall ring 35 goes up and closes the baking oven 51. Next, the flow-control board 52 comes down toward the semiconductor wafer 10, as shown in FIG. 12. The semiconductor wafer 10 is heated by the heater 22 provided in the hot plate 21. The hot plate 21 and heater 22 are shaped and made of a material so as to heat an entire lower surface of the semiconductor wafer 10 uniformly.
While the semiconductor wafer 10 is heated by the hot plate 21, a purge gas (for example, N2 gas) is introduced through the gas-introducing path 36 and the aperture 54 of the flow-control board 52 into the baking oven 51. The purge gas is flowing radially from an area adjacent the center of the wafer 10 toward an area adjacent the peripheral edge of the semiconductor wafer 10, and is exhausted through the gas-exhaust paths 39. The purge gas is in contact with a cooling pipe 37a and is cooled in the gas-introducing path 36 to have a temperature, which is lower than that of the hot plate 21.
The optimum temperatures of the hot plate 21 and purge gas are determined based on measured data of the resist pattern after its baking treatment. That is because the optimum temperatures vary in response to many factors, including a shape and a size of the baking oven 51; a material and widths of the resist pattern on the wafer 10; a degree of heat-flow; the numbers, diameters, positions of the gas-introducing path 36 and gas-exhaust paths 39; and a composition, a flow rate, a flowing route of the purge gas. The chiller 37 arranged at the gas-introducing path 36 can be controlled in accordance with detection results of the sensor 23 and/or other sensors, which may be arranged adjacent the gas-introducing path 36.
According to the apparatus 4, the gas-introducing path 36 and aperture 54 of the flow-control board 52 are arranged directly above the center of the semiconductor wafer 10; and the gas-exhaust paths 39 are arranged at regions adjacent the peripheral edge of the semiconductor wafer 10 in the lower cover 32. Therefore, the purge gas is mainly flowing radially as shown by arrows in
The temperature of the purge gas, which is cooled before being introduced into the baking oven 51, is increased gradually above the semiconductor wafer 10, and then is exhausted through the gas-exhaust paths 39. The temperature of the purge gas is higher at a region adjacent the peripheral edge of the semiconductor wafer in which the purge gas than at a region adjacent the center of the semiconductor wafer 10. The distribution or ranging of the temperature of the purge gas is gradual. As a result, the resist pattern formed at a region adjacent the peripheral edge of the wafer 10 may be changed in size (shrunken) more remarkably as compared to that by a conventional method. In other words, the resist pattern is changed in size at a uniform rate on the semiconductor wafer 10 entirely. Preferably, the outer region of the semiconductor wafer 10 has a temperature 1-2° C. higher than the inner region.
When the baking treatment is completed, the valves 38 and 40 are closed and the inner-wall ring 35 is moved to its lower position. After that, the semiconductor wafer 10 is taken out from the wafer-introducing opening 14.
As described above, according to the fourth preferred embodiment, while the semiconductor wafer 10 is heated entirely by the hot plate 21, the purge gas is cooled by the chiller 37 and is applied onto the upper surface of the semiconductor wafer 10. The gas-introducing paths 36 and gas-exhaust paths 39 are arranged at regions adjacent the center and the peripheral edge of the semiconductor wafer 10, respectively.
The temperature of the semiconductor wafer 10 is higher at around the peripheral edge than around the center thereof. As a result, change rate of size of a resist pattern is made equally on the entire surface of the wafer 10; and therefore, ICs or LSIs formed on the wafer 10 can be fabricated with a higher reliability. As compared to the second preferred embodiment, a flow direction of the purge gas can be controlled precisely using the flow control board 52 with the aperture 54 and shutter 55. The size of the aperture 54 may be controlled in accordance with the temperature of the semiconductor wafer 10, as a result, reliability of ICs or LSIs to be fabricated gets higher.
The flow-control board 52 and lift mechanism 53 are applicable to the apparatus 1 according to the first preferred embodiment.
Fifth Preferred Embodiment
According to this embodiment, a shutter 55 is closed when a heating operation to a semiconductor wafer 10 is started, and then, is closed when a purge gas is introduced into the baking oven 61.
The apparatus 5 includes a flow-control board 52, which is used to control a flow direction of a purge gas in a baking oven 61; a lift mechanism 53 which rises and falls the flow-control board 52; and a temperature sensor 56 which detects a temperature at an upper surface of the semiconductor wafer 10. The flow-control board 52 is arranged above a semiconductor wafer 10 in the baking oven 61. The flow-control board 52 is provided at its center with an opening 44, through which a purge gas is passing onto the semiconductor wafer 10, and with a shutter 55.
The shutter 55 is arranged at the aperture 54 of the flow-control board 52 to adjust an aperture size thereof. The shutter 55 is controlled in accordance with a detection result of the sensor 56. For example, the aperture formed by the shutter 55 is controlled to be wider when the temperature at the upper surface of the semiconductor wafer 10 is detected to be high. The shutter 55 may be controlled in accordance with a material or composition of the resist pattern formed on the wafer 10. A shrink rate of a resist pattern may vary according to its composition and/or quality.
As shown in
The shape of the flow-control board 52; the shape position and number of the opening 54; the structure of the shutter 55; and the number of the sensor 56 are not limited by this embodiment.
As shown in
As shown in
As shown in
In a baking treatment, the semiconductor wafer 10 is set at the wafer holder 25 in the baking oven 61 then, the inner-wall ring 35 goes up and closes the baking oven 61. Next, the flow-control board 52 comes down toward the semiconductor wafer 10, as shown in FIG. 16. The semiconductor wafer 10 is heated by the heater 22 provided in the hot plate 21. At this time, the shutter 55 is maintained to be closed. The hot plate 21 and heater 22 are shaped and made of a material so as to heat an entire lower surface of the semiconductor wafer 10 uniformly.
After a predetermined period of time since the heating operation with the hot plate 21 is started, the shutter 55 is opened to introduce a purge gas (for example, N2 gas) through the gas-introducing path 36 and the aperture 54 of the flow-control board 52 into the baking oven 61. The shutter 55 may be opened in response to detection result of the sensor 23. In the baking oven 61, the purge gas is flowing radially from an area adjacent the center of the wafer 10 toward an area adjacent the peripheral edge of the semiconductor wafer 10, and is exhausted through the gas-exhaust paths 39. The purge gas is in contact with a cooling pipe 37a and is cooled in the gas-introducing path 36 to have a temperature, which is lower than that of the hot plate 21.
The optimum temperatures of the hot plate 21 and purge gas are determined based on measured data of the resist pattern after its baking treatment. That is because the optimum temperatures vary in response to many factors, including a shape and a size of the baking oven 61; a material and widths of the resist pattern on the wafer 10; a degree of heat-flow; the numbers, diameters, positions of the gas-introducing path 36 and gas-exhaust paths 39; and a composition, a flow rate, a flowing route of the purge gas. The chiller 37 arranged at the gas-introducing path 36 can be controlled in accordance with detection results of the sensor 23 and/or other sensors, which may be arranged adjacent the gas-introducing path 36.
According to the apparatus 5, the gas-introducing path 36 and aperture 54 of the flow-control board 52 are arranged directly above the center of the semiconductor wafer 10; and the gas-exhaust paths 39 are arranged at regions adjacent the peripheral edge of the semiconductor wafer 10 in the lower cover 32. Therefore, the purge gas is mainly flowing radially as shown by arrows in
The temperature of the purge gas, which is cooled before being introduced into the baking oven 61, is increased gradually above the semiconductor wafer 10, and then is exhausted through the gas-exhaust paths 39. The temperature of the purge gas is higher at a region adjacent the peripheral edge of the semiconductor wafer in which the purge gas than at a region adjacent the center of the semiconductor wafer 10. The distribution or ranging of the temperature of the purge gas is gradual. As a result, the resist pattern formed at a region adjacent the peripheral edge of the wafer 10 may be changed in size (shrunken) more remarkably as compared to that by a conventional method. In other words, the resist pattern is changed in size at a uniform rate on the semiconductor wafer 10 entirely. Preferably, the outer region of the semiconductor wafer 10 has a temperature 1-2° C. higher than the inner region.
When the baking treatment is completed, the valves 38 and 40 are closed and the inner-wall ring 35 is moved to its lower position. After that, the semiconductor wafer 10 is taken out from the wafer-introducing opening 14.
As described above, according to the fifth preferred embodiment, while the semiconductor wafer 10 is heated entirely by the hot plate 21, the purge gas is cooled by the chiller 37 and is applied onto the upper surface of the semiconductor wafer 10. The gas-introducing paths 36 and gas-exhaust paths 39 are arranged at regions adjacent the center and the peripheral edge of the semiconductor wafer 10, respectively.
The temperature of the semiconductor wafer 10 is higher at around the peripheral edge than around the center thereof. As a result, change rate of size of a resist pattern is made equally on the entire surface of the wafer 10; and therefore, ICs or LSIs formed on the wafer 10 can be fabricated with a higher reliability. As compared to the second preferred embodiment, a flow direction of the purge gas can be controlled precisely using the flow control board 52 with the aperture 54 and shutter 55. The size of the aperture 54 and open timing thereof may be controlled in accordance with the temperature of the semiconductor wafer 10, as a result, reliability of ICs or LSIs to be fabricated gets higher.
The flow-control board 52 and lift-mechanism 53 are applicable to the apparatus 1 according to the first preferred embodiment.
Sixth Preferred Embodiment
The apparatus 6 includes a flow-control board 42 which is used to control a flow direction of a purge gas in a baking oven 41. The flow-control board 42 is arranged above a semiconductor wafer 10 in the baking oven 41. The apparatus 6 also includes a lift mechanism 43 which rises and falls the flow-control board 42. The flow-control board 42 is provided at its center with an aperture or opening 44, through which a purge gas is passing onto the semiconductor wafer 10.
The apparatus 6 includes a heater and/or chiller 72 to heat and/or cool the flow-control board 42, a controller (not shown) which controls the heater 72, and a temperature sensor 73 which detects a temperature at an upper surface of the semiconductor wafer 10. The flow-control board 42 is heated or cooled by the heater 72 within a period of time between the treated semiconductor is taken out and a new one is introduced. In other words, the flow-control board 42 is controlled in temperature to have an original or optimum value after a baking process. In this embodiment, the flow-control board 42 is heated, because the purge gas is cooled while the baking treatment is carried out.
According to this embodiment, the flow-control board 42 is controlled in temperature at the same value before starting a baking treatment. The quality of size and shape of the resist pattern can be uniform or reliable from wafer to wafer. As a result, ICs or LSIs fabricated from such wafers are reliable as well.
In a baking treatment, the semiconductor wafer 10 is set at the wafer holder 25 in the baking oven 71 then, the inner-wall ring 35 goes up and closes the baking oven 71. Next, the flow-control board 42 comes down toward the semiconductor wafer 10, as shown in FIG. 19. The semiconductor wafer 10 is heated by the heater 22 provided in the hot plate 21. The hot plate 21 and heater 22 are shaped and made of a material so as to heat an entire lower surface of the semiconductor wafer 10 uniformly.
While the semiconductor wafer 10 is heated by the hot plate 21, a purge gas (for example, N2 gas) is introduced through the gas-introducing path 36 and the opening 44 of the flow-control board 42 into the baking oven 71. The purge gas is flowing radially from an area adjacent the center of the wafer 10 toward an area adjacent the peripheral edge of the semiconductor wafer 10, and is exhausted through the gas-exhaust paths 39. The purge gas is in contact with a cooling pipe 37a and is cooled in the gas-introducing path 36 to have a temperature, which is lower than that of the hot plate 21.
The optimum temperatures of the hot plate 21 and purge gas are determined based on measured data of the resist pattern after its baking treatment. That is because the optimum temperatures vary in response to many factors, including a shape and a size of the baking oven 71; a material and widths of the resist pattern on the wafer 10; a degree of heat-flow; the numbers, diameters, positions of the gas-introducing path 36 and gas-exhaust paths 39; and a composition, a flow rate, a flowing route of the purge gas. The chiller 37 arranged at the gas-introducing path 36 can be controlled in accordance with an output of the temperature sensor 23 or other sensors, which may be arranged adjacent the gas-introducing path 36.
According to the apparatus 6, the gas-introducing path 36 and opening 44 of the flow-control board 42 are arranged directly above the center of the semiconductor wafer 10; and the gas-exhaust paths 39 are arranged at regions adjacent the peripheral edge of the semiconductor wafer 10 in the lower cover 32. Therefore, the purge gas is mainly flowing radially as shown by arrows in
The temperature of the purge gas, which is cooled before being introduced into the baking oven 71, is increased gradually above the semiconductor wafer 10, and then is exhausted through the gas-exhaust paths 39. The temperature of the purge gas is higher at a region adjacent the peripheral edge of the semiconductor wafer in which the purge gas than at a region adjacent the center of the semiconductor wafer 10. The distribution or ranging of the temperature of the purge gas is gradual. As a result, the resist pattern formed at a region adjacent the peripheral edge of the wafer 10 may be changed in size (shrunken) more remarkably as compared to that by a conventional method. In other words, the resist pattern is changed in size at a uniform rate on the semiconductor wafer 10 entirely. Preferably, the outer region of the semiconductor wafer 10 has a temperature 1-2° C. higher than the inner region.
When the baking treatment is completed, the valves 38 and 40 are closed and the inner-wall ring 35 is moved to its lower position. After that, the semiconductor wafer 10 is taken out from the wafer-introducing opening 34.
As described above, according to the sixth preferred embodiment, while the semiconductor wafer 10 is heated entirely by the hot plate 21, the purge gas is cooled by the chiller 17 and is applied onto the upper surface of the semiconductor wafer 10. The gas-introducing paths 36 and gas-exhaust paths 39 are arranged at regions adjacent the center and the peripheral edge of the semiconductor wafer 10, respectively. The temperature of the semiconductor wafer 10 is higher at around the peripheral edge than around the center thereof. As a result, change rate of size of a resist pattern is made equally on the entire surface of the wafer 10; and therefore, ICs or LSIs formed on the wafer 10 can be fabricated with a higher reliability. As compared to the second preferred embodiment, a flow direction of the purge gas can be controlled precisely using the flow control board 42 with the center opening 44.
As described above, according to this embodiment, the flow-control board 42 is controlled in temperature at the same value before starting a baking treatment. The quality of size and shape of the resist pattern can be uniform or reliable from wafer to wafer. As a result, ICs or LSIs fabricated from such wafers are reliable as well.
The flow-control board 42 and lift mechanism 43 are applicable to the apparatus 1 according to the first preferred embodiment.
Seventh Preferred Embodiment
As shown in
As shown in
As shown in
As shown in
As shown in
Although in
In a baking treatment, the semiconductor wafer 10 is heated by the heater 22 provided in the hot plate 21. The hot plate 21 and heater 22 are shaped and made of a material so as to heat an entire lower surface of the semiconductor wafer 10 uniformly. On the semiconductor wafer 10, portions adjacent the peripheral edge are heated by the upper hot plate 90. While the semiconductor wafer 10 is heated by the hot plates 21 and 90, a purge gas (for example, N2 gas) is introduced through the gas-introducing path 86 into the baking oven 81. The purge gas is exhausted through the gas-exhaust path 88. Preferably, the outer region of the semiconductor wafer 10 has a temperature 1-2° C. higher than the inner region.
When the baking treatment is completed, the valves 87 and 89 are closed and the inner-wall ring 85 is moved to its lower position. After that, the semiconductor wafer 10 is taken out from the wafer-introducing opening 84.
As described above, according to the seventh preferred embodiment, while the lower surface of the semiconductor wafer 10 is heated entirely by the hot plate 21, the upper surface of the wafer 10 is heated at its outer portions (peripheral edge) by the upper hot plate 90. The temperature of the semiconductor wafer 10 is higher at around the peripheral edge than around the center thereof. As a result, change rate of size of a resist pattern is made equally on the entire surface of the wafer 10; and therefore, ICs or LSIs formed on the wafer 10 can be fabricated with a higher reliability.
The upper hot plate 90 is applicable to the before described apparatus 1-6 according to the first to sixth preferred embodiments.
Eighth Preferred Embodiment
As shown in
As shown in
The upper cover 83 is provided with a gas-exhaust path 88, through which a purge gas is exhausted out of the baking oven 101. The upper cover 83 is also provided with a valve 89 in the gas-exhaust path 88 to open and close the gas-exhaust path 88. The number, shape and arrangement of the gas-exhaust path 88 are not limited by this embodiment as long as the purge gas is exhausted out of the baking oven 101.
As shown in
Although in
In a baking treatment, the semiconductor wafer 10 is heated by the heater 103 provided in the hot plate 102. The hot plate 102 and heater 103 are shaped and made of a material so as to heat an entire lower surface of the semiconductor wafer 10 uniformly. On the semiconductor wafer 10, portions adjacent the center thereof is cooled by the cooling pipe 105. While the semiconductor wafer 10 is heated by the heater 103 and cooled by the cooling pipe 105, a purge gas (for example, N2 gas) is introduced through the gas-introducing path 86 into the baking oven 101. The purge gas is exhausted through the gas-exhaust path 88. According to this embodiment, the semiconductor wafer 10 is cooled at its inner regions while a baking treatment is carried out, so that the semiconductor wafer 10 has a higher temperature at an outer region than the inner region. That is, a temperature gradient is provided to the semiconductor wafer 10 while a baking treatment. Preferably, the outer region of the semiconductor wafer 10 has a temperature 1-2° C. higher than the inner region.
When the baking treatment is completed, the valves 87 and 89 are closed and the inner-wall ring 85 is moved to its lower position. After that, the semiconductor wafer 10 is taken out from the wafer-introducing opening 84.
As described above, according to the eighth preferred embodiment, while the lower surface of the semiconductor wafer 10 is heated entirely by the heater 103, the inner portion adjacent the center of the wafer 10 is cooled by the cooling pipe 105. The temperature of the semiconductor wafer 10 is higher at around the peripheral edge than around the center thereof. As a result, change rate of size of a resist pattern is made equally on the entire surface of the wafer 10; and therefore, ICs or LSIs formed on the wafer 10 can be fabricated with a higher reliability.
The hot plate 102 is applicable to the before described apparatuses 1-7 according to the first to seventh embodiments.
Ninth Preferred Embodiment
The hot plate 110 includes a first wafer heater 111, a first temperature sensor 112, a second wafer heater 113 and a second temperature sensor 114. The first wafer heater 111 heats an outer region of a semiconductor wafer 10. The first sensor 112 detects a temperature at an outer region of the semiconductor wafer 10. The second wafer heater 113 heats an inner region of a semiconductor wafer 10. The second sensor 114 detects a temperature at an inner region of the semiconductor wafer 10. The outer region corresponds to a region adjacent the peripheral edge of the semiconductor wafer 10, while the inner region corresponds to a region adjacent the center of the semiconductor wafer.
The baking apparatus according to this embodiment includes a temperature controller 116, which controls a voltage level to be applied to the first wafer heater 111 in accordance with a detection result of the first temperature sensor 112. The baking apparatus further includes a temperature controller 115, which controls a voltage level to be applied to the second wafer heater 113 in accordance with a detection result of the second temperature sensor 114.
As described above, according to the ninth preferred embodiment, the hot plate 110 is divided into two parts of an outer region and an inner region, which are heated by the first and second heaters 111 and 113, respectively. The temperature of the inner region is controlled to be lower than the outer region. Preferably, the outer region of the semiconductor wafer 10 has a temperature 1-2° C. higher than the inner region.
In a baking treatment, the semiconductor wafer 10 is heated by the heaters 111 and 113 provided in the hot plate 110. The hot plate 110 and heaters 111 and 113 are shaped and made of a material so that the semiconductor wafer 10 has a higher temperature at an outer region adjacent the peripheral edge than at an inner region adjacent the center thereof. While the semiconductor wafer 10 is heated by the heaters 111 and 113, a purge gas (for example, N2 gas) is introduced into a baking oven (101). The purge gas is exhausted through the gas-exhaust path 88. According to this embodiment, a temperature gradient is provided to the semiconductor wafer 10 while a baking treatment.
As described above, according to the ninth preferred embodiment, the hot plate 110 is controlled in temperature so that the inner region has a lower temperature than the outer region. Therefore, the temperature of the semiconductor wafer 10 is higher at around the peripheral edge than around the center thereof. As a result, change rate of size of a resist pattern is made equally on the entire surface of the wafer 10; and therefore, ICs or LSIs formed on the wafer 10 can be fabricated with a higher reliability.
The hot plate 110 is also applicable to the baking apparatuses 1-7, according to the first to seventh preferred embodiments. The hot plate 110 may includes three heaters or more so that the hot plate 110 is controlled in temperature for each of three or more different regions independently.
Tenth Preferred Embodiment
The hot plate 120 includes a first wafer heater 111, a first temperature sensor 112, a second wafer heater 113 and a second temperature sensor 114. The first wafer heater 111 heats an outer region of a semiconductor wafer 10. The first sensor 112 detects a temperature at an outer region of the semiconductor wafer 10. The second wafer heater 113 heats an inner region of a semiconductor wafer 10. The second sensor 114 detects a temperature at an inner region of the semiconductor wafer 10. The outer region corresponds to a region adjacent the peripheral edge of the semiconductor wafer 10, while the inner region corresponds to a region adjacent the center of the semiconductor wafer.
The hot plate 120 also includes a heat insulating material 121, which is arranged between the first and second heaters 111 and 113. The baking apparatus according to this embodiment includes a temperature controller 116, which controls a voltage level to be applied to the first wafer heater 111 in accordance with a detection result of the first temperature sensor 112. The baking apparatus further includes a temperature controller 115, which controls a voltage level to be applied to the second wafer heater 113 in accordance with a detection result of the second temperature sensor 114.
As described above, according to the tenth preferred embodiment, the hot plate 110 is divided into two parts of an outer region and an inner region, which are heated by the first and second heaters 111 and 113, respectively. The temperature of the inner region is controlled to be lower than the outer region. Preferably, the outer region of the semiconductor wafer 10 has a temperature 1-2° C. higher than the inner region.
Eleventh Preferred Embodiment
The hot plate 130 includes a first portion 131 and a second portion 132, which form an outer region and an inner region of the hot plate 130, respectively. The first portion 131 is made of a material having a higher heat conductivity than the second portion 132. The hot plate 130 also includes a wafer heater 133, a first temperature sensor 135, and a second temperature sensor 134. The wafer heater 133 heats an upper surface of the hot plate 130 entirely and uniformly. The first sensor 135 is arranged at the first portion 131 to detect a temperature thereat. The second sensor 134 detects a temperature at an inner region of the semiconductor wafer 10.
According to this embodiment, the outer portion 131 of the hot plate 120 has a higher heat conductivity, so that the our region of the hot plate 120 and a region adjacent the peripheral edge of the semiconductor wafer is heated at a higher temperature than the inner portion 133.
As described above, according to the eleventh preferred embodiment, the hot plate 130 is controlled in temperature so that the inner region has a lower temperature than the outer region. Therefore, the temperature of the semiconductor wafer 10 is higher at around the peripheral edge than around the center thereof. As a result, change rate of size of a resist pattern is made equally on the entire surface of the wafer 10; and therefore, ICs or LSIs formed on the wafer 10 can be fabricated with a higher reliability.
According to the eleventh preferred embodiment, the hot plate 130 is divided into two parts of an outer region and an inner region, which are made of materials having different heat conductivities. The hot plate 130 can be formed with three parts that are made of materials having different heat conductivities. The parts 131 and 132 may be designed to be exchangeable from the hot plate 130. The hot plate 130 is applicable to the baking apparatuses 1-7 according to the first to seventh preferred embodiments.
Twelfth Preferred Embodiment
The hot plate 140 includes a first wafer heater 141, a first temperature sensor 143, a second wafer heater 142 and a second temperature sensor 144. The first wafer heater 141 heats an outer region of a semiconductor wafer 10. The first sensor 143 detects a temperature at an outer region of the hot plate 140 facing a region adjacent the peripheral edge of the semiconductor wafer 10. The second wafer heater 142 heats an inner region of a semiconductor wafer 10. The second sensor 144 detects a temperature at an inner region of the hot plate 140 facing a region adjacent the center of the semiconductor wafer 10.
The baking apparatus according to this embodiment includes a first variable transformer 145, a second variable transformer 146 and a temperature controller 147. The first variable transformer 145 controls a voltage to be applied to the first wafer heater 141. The second variable transformer 146 controls a voltage to be applied to the second wafer heater 142. The temperature controller 147 is connected to the first and second variable transformers 145 and 146. The temperature controller 147 controls output voltage levels of the first and second variable transformer 145 and 146 in response to detection results of the first and second sensors 143 and 144, respectively. A heat insulating material 148 may be provided between the first and second heaters 141 and 142, as shown in FIG. 29.
As described above, according to the twelfth preferred embodiment, the hot plate 140 is divided into two parts of an outer region and an inner region, which are heated by the first and second heaters 141 and 142, respectively. The temperature of the inner region is controlled to be lower than the outer region. Preferably, the outer region of the semiconductor wafer 10 has a temperature 1-2° C. higher than the inner region.
As described above, according to the twelfth preferred embodiment, the hot plate 140 is controlled in temperature so that the inner region has a lower temperature than the outer region. Therefore, the temperature of the semiconductor wafer 10 is higher at around the peripheral edge than around the center thereof. As a result, change rate of size of a resist pattern is made equally on the entire surface of the wafer 10; and therefore, ICs or LSIs formed on the wafer 10 can be fabricated with a higher reliability.
According to the twelfth preferred embodiment, the hot plate 140 is divided into two parts of an outer region and an inner region, which are heated by the different heaters 141 and 142, respectively. The hot plate 140 can be formed with three parts that are heated by different heaters independently. The hot plate 140 is applicable to the baking apparatuses 1-7 according to the first to seventh preferred embodiments. In addition, upper and lower hot plates may be controlled by a single controller to have different temperatures.
Thirteenth Preferred Embodiment
The hot plate 150 includes a first wafer heater 151, a first temperature sensor 153, a second wafer heater 152 and a second temperature sensor 154. The first wafer heater 151 heats an outer region of a semiconductor wafer 10. The first sensor 153 detects a temperature at an outer region of the hot plate 150 facing a region adjacent the peripheral edge of the semiconductor wafer 10. The second wafer heater 152 heats an inner region of a semiconductor wafer 10. The second sensor 154 detects a temperature at an inner region of the hot plate 150 facing a region adjacent the center of the semiconductor wafer 10.
The baking apparatus according to this embodiment includes a first switching device 155, a second switching device 156 and a temperature controller 147. The first switching device 145 turns on and off to control supply of a voltage signal to the first wafer heater 151. The second switching device 146 turns on and off to control supply of a voltage signal to the second wafer heater 151. The temperature controller 147 is connected to the first and second switching devices 155 and 156. The temperature controller 147 controls the switches 155 and 156 in accordance with detection results of the first and second sensors 153 and 154, respectively. A heat insulating material 158 may be provided between the first and second heaters 151 and 152, as shown in FIG. 30.
As described above, according to the thirteenth preferred embodiment, the hot plate 150 is divided into two parts of an outer region and an inner region, which are heated by the first and second heaters 151 and 152, respectively. The temperature of the inner region is controlled to be lower than the outer region. Preferably, the outer region of the semiconductor wafer 10 has a temperature 1-2° C. higher than the inner region.
As described above, according to the thirteenth preferred embodiment, the hot plate 150 is controlled in temperature so that the inner region has a lower temperature than the outer region. Therefore, the temperature of the semiconductor wafer 10 is higher at around the peripheral edge than around the center thereof. As a result, change rate of size of a resist pattern is made equally on the entire surface of the wafer 10; and therefore, ICs or LSIs formed on the wafer 10 can be fabricated with a higher reliability.
The hot plate 150 can be formed with three parts that are heated by different heaters independently. The hot plate 150 is applicable to the baking apparatuses 1-7 according to the first to seventh preferred embodiments. In addition, upper and lower hot plates may be controlled by a single controller to have different temperatures, in the same manner as the seventh preferred embodiment.
Some of the above-described embodiments can be combined to form other types of baking apparatuses.
Claims
1. An apparatus for baking a semiconductor wafer having a resist pattern thereon, comprising:
- a baking oven in which the semiconductor wafer is placed and heated;
- a first hot plate which is provided in the baking oven to heat an entire bottom surface of the semiconductor wafer;
- a temperature sensor located adjacent to said first hot plate;
- a gas supply unit which comprises a gas introducing path, through which the purge gas is introduced into the baking oven, and a gas exhaust path, through which the purge gas is exhausted out of the baking oven; and
- a gas temperature controller which controls a temperature of the purge gas in accordance with an output of the temperature sensor, in order that the purge gas flowing around a peripheral edge or outer portion of the wafer has a higher temperature than that flowing around the center or inner portion of the wafer.
2. An apparatus according to claim 1, wherein
- the gas introducing path is arranged adjacent the center of the semiconductor wafer,
- the gas exhaust path is arranged adjacent the peripheral edge of the semiconductor wafer, and
- the gas temperature controller comprises a gas cooler arranged adjacent the gas introducing path to cool the purge gas to be introduced into the baking oven.
3. An apparatus according to claim 1, further comprising:
- a second hot plate which heats a region adjacent the peripheral edge of an upper surface of the semiconductor wafer.
4. An apparatus according to claim 2, wherein said temperature sensor is located adjacent to a center of said first hot plate.
5. An apparatus according to claim 2, wherein said temperature sensor is located at a center of said first hot plate.
6. An apparatus according to claim 1, wherein said temperature sensor is located adjacent to a center of said first hot plate.
7. An apparatus according to claim 1, wherein said temperature sensor is located at a center of said first hot plate.
8. A method for baking a semiconductor wafer having a resist pattern thereon, comprising:
- setting the semiconductor wafer in a baking oven;
- heating an entire bottom surface of the semiconductor wafer using a first hot plate;
- detecting and outputting a temperature value with a temperature sensor located adjacent to said first hot plate;
- supplying a purge gas onto an upper surface of the semiconductor wafer; and
- controlling a temperature of the purge gas according to the temperature value output of the temperature sensor, in order that the purge gas flowing around a peripheral edge of the semiconductor wafer has a higher temperature than that flowing around the center of the wafer.
9. A method according to claim 8, wherein
- the purge gas is introduced from a portion adjacent the center of the semiconductor wafer,
- the purge gas is exhausted from a portion adjacent the peripheral edge of the semiconductor wafer, and
- the purge gas is cooled before being introducing into the baking oven.
10. A method according to claim 8, further comprising:
- heating a region adjacent the peripheral edge of an upper surface of the semiconductor wafer.
11. A method according to claim 9, wherein said step of detecting and outputting a temperature value with a temperature sensor includes positioning the temperature sensor adjacent to a center of the first hot plate.
12. A method according to claim 9, wherein said step of detecting and outputting a temperature value with a temperature sensor includes positioning the temperature sensor at a center of the first hot plate.
13. A method according to claim 8, wherein said step of detecting and outputting a temperature value with a temperature sensor includes positioning the temperature sensor adjacent to a center of the first hot plate.
14. A method according to claim 8, wherein said step of detecting and outputting a temperature value with a temperature sensor includes positioning the temperature sensor at a center of the first hot plate.
15. An apparatus for baking a semiconductor wafer having a resist pattern thereon, comprising:
- a baking oven in which the semiconductor wafer is placed and heated;
- a first hot plate which is provided in the baking oven to heat an entire bottom surface of the semiconductor wafer;
- a temperature sensor located in the baking oven;
- a gas supply unit which comprises a gas introducing path, through which the purge gas is introduced into the baking oven, and a gas exhaust path, through which the purge gas is exhausted out of the baking oven; and
- a gas temperature controller, the temperature sensor being positioned in the baking oven and the gas temperature controller controlling a temperature of the purge gas in accordance with an output of the temperature sensor, such that the purge gas flowing around a peripheral edge or outer portion of the wafer has a higher temperature than that flowing around the center or inner portion of the wafer.
16. An apparatus according to claim 15, wherein the temperature sensor is positioned in relation to the first hot plate and the controller controlling the temperature of the purge gas according to the temperature value output of the temperature sensor, such that the purge gas flowing around a peripheral edge of the semiconductor wafer has a higher temperature than that flowing around the center of the wafer.
17. A method for baking a semiconductor wafer having a resist pattern thereon, comprising:
- setting the semiconductor wafer in a baking oven;
- heating an entire bottom surface of the semiconductor wafer using a first hot plate;
- detecting and outputting a temperature value with a located adjacent to said first hot plate;
- supplying a purge gas onto an upper surface of the semiconductor wafer; and
- positioning a temperature sensor in the baking oven and controlling a temperature of the purge gas according to a temperature value output of the temperature sensor, such that the purge gas flowing around a peripheral edge of the semiconductor wafer has a higher temperature than that flowing around the center of the wafer.
18. A method according to claim 17, wherein said positioning and controlling includes positioning the temperature sensor in relation to the first hot plate and controlling the temperature of the purge gas according to a temperature value output of the temperature sensor, such that the purge gas flowing around a peripheral edge of the semiconductor wafer has a higher temperature than that flowing around the center of the wafer.
Type: Grant
Filed: Jul 18, 2002
Date of Patent: Jan 4, 2005
Patent Publication Number: 20030057198
Assignee: OKI Electric Industry Co., Ltd. (Tokyo)
Inventors: Shouzou Kobayashi (Tokyo), Takamitsu Furukawa (Tokyo), Keisuke Tanaka (Tokyo), Kouhei Shimoyama (Tokyo), Akira Watanabe (Tokyo), Tadashi Nishimuro (Tokyo), Koki Muto (Tokyo), Azusa Yanagisawa (Tokyo), Katsuo Oshima (Tokyo)
Primary Examiner: Shawntina Fuqua
Attorney: Rabin & Berdo, PC
Application Number: 10/197,598