Patents by Inventor Katsuo Yamada

Katsuo Yamada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230331357
    Abstract: The present disclosure provides an autonomous cruising system capable of improving an accuracy of identifying description of a sign. The autonomous cruising system includes processing circuitry. The processing circuitry acquires a first image including a buoy from a camera installed in a ship. The processing circuitry identifies a position of the buoy inside the first image. The processing circuitry acquires a second image corresponding to a partial area of the first image including the position of the buoy, and the second image is higher in resolution than the first image. The processing circuitry identifies description of a sign of the buoy based on the second image.
    Type: Application
    Filed: June 22, 2023
    Publication date: October 19, 2023
    Inventors: Yuichi HARA, Katsuo YAMADA
  • Publication number: 20220352093
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory opening fill structures located within a respective memory opening vertically extending through the alternating stack in a memory array region, and support pillar structures vertically extending through the alternating stack. Each of the memory opening fill structures includes a respective vertical semiconductor channel and a respective memory film that contacts each layer within the alternating stack. Each of the support pillar structures includes a respective dummy vertical semiconductor channel, a respective dummy memory film, and at least one respective dielectric spacer material portion laterally surrounding the respective dummy memory film and interposed between the electrically conductive layers and the respective dummy memory film.
    Type: Application
    Filed: June 13, 2022
    Publication date: November 3, 2022
    Inventors: Katsuo Yamada, Kakeru Tamai, Akira Iwasaki, Akira Fukunaga, Koichi Matsuno
  • Publication number: 20190204416
    Abstract: A target object detecting device is provided, which may include an acquisition part, a generation part, and a detecting part. The acquisition part may acquire echo signals from target objects around a ship. The generation part may generate a first echo image based on the echo signals. The detecting part may input the first echo image into a model built by a program implementing a machine learning algorithm, and may detect a first target object that is a target object other than a ship corresponding to the model, based on an output from the model.
    Type: Application
    Filed: December 27, 2018
    Publication date: July 4, 2019
    Inventors: Katsuyuki Yanagi, Shinsuke Inoue, Katsuo Yamada
  • Patent number: 10115459
    Abstract: An opening is formed through at least one dielectric material layer. A first metallic liner is formed on a bottom surface and sidewalls of the opening by depositing a first metallic material. A metal portion including an elemental metal or an intermetallic alloy of at least two elemental metals is formed on the first metallic liner. A second metallic liner including a second metallic material is formed directly on a top surface of the metal portion. The first metallic material and the second metallic material differ in composition. The first metallic liner and the second metallic liner contact an entirety of all surfaces of the metal portion. The first and second metallic liners can protect the metal portion from a subsequently deposited dielectric material layer, which may be formed as an air-gap dielectric layer after recessing the at least one dielectric material layer.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: October 30, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Katsuo Yamada, Tomoyasu Kakegawa, Peter Rabkin, Jayavel Pachamuthu, Mohan Dunga, Masaaki Higashitani
  • Patent number: 9847249
    Abstract: A stack of layers is formed that includes first, second, and third dielectric layers. Contact plugs are then formed extending through the stack. Then a fourth dielectric layer is formed over the stack and contact plugs and trenches are formed through the fourth and third dielectric layers, extending to the second dielectric layer and exposing contact plugs.
    Type: Grant
    Filed: November 5, 2014
    Date of Patent: December 19, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yuji Takahashi, Takuya Futase, Noritaka Fukuo, Katsuo Yamada, Tomoyasu Kakegawa
  • Patent number: 9799527
    Abstract: Isolation is provided by forming a first trench, depositing a cover layer on the bottom and sidewalls of the first trench, selectively removing the cover layer from the bottom and forming a second trench extending from the bottom of the first trench. The second trench is then substantially filled by thermal oxide formed by oxidation and the first trench is subsequently filled with a deposited dielectric.
    Type: Grant
    Filed: October 21, 2014
    Date of Patent: October 24, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Katsuo Yamada, Yuji Takahashi, Takuya Futase, Noritaka Fukuo, Tomoyasu Kakegawa
  • Patent number: 9685070
    Abstract: An alarm informing device is provided. The alarm informing device receives detection information from one or more sensors and informs an alarm to a user when either one of failure in the one or more sensors and error in the reception of the information from the one or more sensors occurs. The alarm informing device includes a time synchronizing module configured to synchronize an internal clock of the alarm informing device with an internal clock of another alarm informing device, an alarm sound output timing control module configured to control a timing of outputting an alarm sound when the alarm is issued, based on the internal clock of the alarm informing device, and a sound outputter configured to output the alarm sound at the timing controlled by the alarm sound output timing control module.
    Type: Grant
    Filed: April 8, 2015
    Date of Patent: June 20, 2017
    Assignee: Furuno Electric Co., Ltd.
    Inventor: Katsuo Yamada
  • Patent number: 9607997
    Abstract: A wide trench having a width W1 and narrow trenches having a width W2 that is less than W1 are formed in a dielectric layer, the wide trench extending deeper in outer regions than in a central region. A trench modification step changes the width of the wide trench and reduces a depth difference between the outer regions and the central region of the wide trench.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: March 28, 2017
    Assignee: SANDISK TECHNOLOGIES INC.
    Inventors: Katsuo Yamada, Yuji Takahashi, Noritaka Fukuo, Masami Uozaki, Kiyokazu Shishido, Takuya Futase, Shunsuke Watanabe
  • Publication number: 20170069638
    Abstract: A wide trench having a width W1 and narrow trenches having a width W2 that is less than W1 are formed in a dielectric layer, the wide trench extending deeper in outer regions than in a central region. A trench modification step changes the width of the wide trench and reduces a depth difference between the outer regions and the central region of the wide trench.
    Type: Application
    Filed: September 8, 2015
    Publication date: March 9, 2017
    Inventors: Katsuo Yamada, Yuji Takahashi, Noritaka Fukuo, Masami Uozaki, Kiyokazu Shishido, Takuya Futase, Shunsuke Watanabe
  • Patent number: 9466523
    Abstract: Contact holes are constrained to their designated active areas by etch-resistant walls so that they cannot contact adjacent active areas. Etch-resistant walls provide outer limits for any contact hole bending that may occur and thus keep contact holes substantially vertical. Mask openings for contact hole formation may be large so that they overlap etch-resistant walls.
    Type: Grant
    Filed: July 29, 2014
    Date of Patent: October 11, 2016
    Assignee: SanDisk Technologies LLC
    Inventors: Tomoyasu Kakegawa, Takuya Futase, Katsuo Yamada, Keita Kumamoto, Hirotada Tobita
  • Publication number: 20160204059
    Abstract: Trenches are formed partially through a sacrificial layer at locations where bit lines are to be formed with some sacrificial material overlying vias. The trenches are lined with a protective layer and then the trenches are extended to expose vias. Bit lines are formed. Then sacrificial material is removed from between bit lines while portions of the protective layer remain to protect the bit lines.
    Type: Application
    Filed: January 9, 2015
    Publication date: July 14, 2016
    Inventors: Noritaka Fukuo, Takuya Futase, Katsuo Yamada, Yuji Takahashi, Tomoyasu Kakegawa
  • Patent number: 9391081
    Abstract: A first depression and a second depression are formed in an upper surface of a first metal layer. A dielectric layer is formed over the first metal layer. Subsequently, a wide trench is formed in the dielectric layer, the wide trench extending deeper in a first outer region and in a second outer region than in a central region located between the first outer region and the second outer region, the first outer region overlying the first depression and the second outer region overlying the second depression.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: July 12, 2016
    Assignee: SanDisk Technologies LLC
    Inventors: Kiyokazu Shishido, Takuya Futase, Noritaka Fukuo, Yuji Takahashi, Shunsuke Watanabe, Katsuo Yamada, Masami Uozaki
  • Publication number: 20160126179
    Abstract: A stack of layers is formed that includes first, second, and third dielectric layers. Contact plugs are then formed extending through the stack. Then a fourth dielectric layer is formed over the stack and contact plugs and trenches are formed through the fourth and third dielectric layers, extending to the second dielectric layer and exposing contact plugs.
    Type: Application
    Filed: November 5, 2014
    Publication date: May 5, 2016
    Inventors: Yuji Takahashi, Takuya Futase, Noritaka Fukuo, Katsuo Yamada, Tomoyasu Kakegawa
  • Publication number: 20160111493
    Abstract: Isolation is provided by forming a first trench, depositing a cover layer on the bottom and sidewalls of the first trench, selectively removing the cover layer from the bottom and forming a second trench extending from the bottom of the first trench. The second trench is then substantially filled by thermal oxide formed by oxidation and the first trench is subsequently filled with a deposited dielectric.
    Type: Application
    Filed: October 21, 2014
    Publication date: April 21, 2016
    Inventors: Katsuo Yamada, Yuji Takahashi, Takuya Futase, Noritaka Fukuo, Tomoyasu Kakegawa
  • Publication number: 20160035738
    Abstract: Contact holes are constrained to their designated active areas by etch-resistant walls so that they cannot contact adjacent active areas. Etch-resistant walls provide outer limits for any contact hole bending that may occur and thus keep contact holes substantially vertical. Mask openings for contact hole formation may be large so that they overlap etch-resistant walls.
    Type: Application
    Filed: July 29, 2014
    Publication date: February 4, 2016
    Inventors: Tomoyasu Kakegawa, Takuya Futase, Katsuo Yamada, Keita Kumamoto, Hirotada Tobita
  • Publication number: 20150332953
    Abstract: Air gaps are formed between conductive metal lines that have an inner barrier layer and an outer barrier layer. An etch step to remove sacrificial material is performed under a first set of process conditions producing a byproduct that suppresses further etching. A byproduct removal step performed under a second set of process conditions removes the byproduct.
    Type: Application
    Filed: September 25, 2014
    Publication date: November 19, 2015
    Inventors: Takuya Futase, Katsuo Yamada, Tomoyasu Kakegawa, Noritaka Fukuo, Yuji Takahashi
  • Patent number: 9177853
    Abstract: Air gaps are formed between conductive metal lines that have an inner barrier layer and an outer barrier layer. An etch step to remove sacrificial material is performed under a first set of process conditions producing a byproduct that suppresses further etching. A byproduct removal step performed under a second set of process conditions removes the byproduct.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: November 3, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Takuya Futase, Katsuo Yamada, Tomoyasu Kakegawa, Noritaka Fukuo, Yuji Takahashi
  • Publication number: 20150294555
    Abstract: An alarm informing device is provided. The alarm informing device receives detection information from one or more sensors and informs an alarm to a user when either one of failure in the one or more sensors and error in the reception of the information from the one or more sensors occurs. The alarm informing device includes a time synchronizing module configured to synchronize an internal clock of the alarm informing device with an internal clock of another alarm informing device, an alarm sound output timing control module configured to control a timing of outputting an alarm sound when the alarm is issued, based on the internal clock of the alarm informing device, and a sound outputter configured to output the alarm sound at the timing controlled by the alarm sound output timing control module.
    Type: Application
    Filed: April 8, 2015
    Publication date: October 15, 2015
    Inventor: Katsuo Yamada
  • Patent number: 8922429
    Abstract: A pseudo range is corrected with high accuracy using a pseudo range correction method that incorporates carrier smoothing. A code pseudo range correction unit (19) performs carrier smoothing of an L1 code pseudo range (PRL1(i)) by the temporal change (?ADRL1(i)) in an L1 carrier phase, and performs carrier correction of a code ionosphere delay (IPRL1(i)) by the temporal change (?IADRL1(i)) in a carrier ionosphere delay. The code pseudo range correction unit (19) performs ionosphere delay correction by subtracting the corrected ionosphere delay (I?L1sm(i)) from the L1 code pseudo range (PRL1sm(i)) after smoothing processing. At this time, a direction of the delay in the temporal change (?IADRL1(i)) in the carrier ionosphere delay included in the temporal change (?ADRL1(i)) in the L1 carrier phase is matched with a direction of the delay in the temporal change (?IADRL1(i)) in the carrier ionosphere delay used to calculate the corrected ionosphere delay (I?L1sm(i)).
    Type: Grant
    Filed: October 26, 2009
    Date of Patent: December 30, 2014
    Assignee: FURUNO Electric Company Limited
    Inventors: Naomi Fujisawa, Katsuo Yamada, Yoji Goto, Hiraku Nakamura
  • Patent number: 8736489
    Abstract: To provide an art that can improve a performance of a GNSS receiver. A GNSS receiver 100 includes a receiver 1, a navigation message acquiring unit 3, a navigation message processor 5, and a calculator 6. The receiver 1 receives signals from satellites. The navigation message acquiring unit 3 acquires predetermined information in navigation messages contained in the signals received by the receiver. The navigation message processor 5 outputs either one of the same kind of information in the plural different kinds of navigation messages, which is acquired by the navigation message acquiring unit 3. The calculator 6 performs a calculation based on the information outputted from the navigation message processor 5.
    Type: Grant
    Filed: May 27, 2010
    Date of Patent: May 27, 2014
    Assignee: Furuno Electric Company Limited
    Inventors: Yoji Goto, Katsuo Yamada, Naomi Fujisawa, Hiraku Nakamura