Patents by Inventor Katsura Miyashita

Katsura Miyashita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8158472
    Abstract: A SRAM bit cell and an associated method of producing the SRAM bit cell with improved performance and stability is provided. In one configuration, channel mobility of the transistors within the SRAM bit cell may be adjusted to provide improved stability. In order to adjust the channel mobility, a stress memorization technique may be used, a wide spacer may be used, germanium may be implanted on tensile stress silicon nitride, a compressive liner may be used or silicon germanium may be embedded in one or more of the devices in the cell. In another configuration, the gate capacitance of each device within the SRAM bit cell may be adjusted to achieve high SRAM yield. For instance, a thick gate oxide may be used, phosphorous pre-doping may be used or fluorine pre-doping may be used in one or more of the devices within the cell.
    Type: Grant
    Filed: August 23, 2010
    Date of Patent: April 17, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Katsura Miyashita
  • Patent number: 8110874
    Abstract: A hybrid substrate circuit on a common substrate is disclosed. A first circuit formed in a first semiconductor material is isolated via a buried oxide layer from a second circuit formed in a second semiconductor material. The first and second circuits may include CMOS, HEMTs, P-HEMTs, HBTs, radio frequency circuits, MESFETs, and various pFETs and nFETs.
    Type: Grant
    Filed: March 9, 2009
    Date of Patent: February 7, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Katsura Miyashita
  • Publication number: 20110256674
    Abstract: A system and method for ion implantation during semiconductor fabrication. An integrated circuit may be designed with proximately located one-directional transistor gates. A two-way halo ion implantation is performed perpendicularly to the transistor gates in order to embed the dopant into the silicon body on the surface of the semiconductor wafer. The two-way halo both reduces the channeling effect by allowing ion implantation beneath the transistor gate, and reduces the halo shadowing effect resulting from halo implanting which is done parallel to the transistor gates.
    Type: Application
    Filed: June 28, 2011
    Publication date: October 20, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Katsura Miyashita
  • Publication number: 20100314692
    Abstract: A SRAM bit cell and an associated method of producing the SRAM bit cell with improved performance and stability is provided. In one configuration, channel mobility of the transistors within the SRAM bit cell may be adjusted to provide improved stability. In order to adjust the channel mobility, a stress memorization technique may be used, a wide spacer may be used, germanium may be implanted on tensile stress silicon nitride, a compressive liner may be used or silicon germanium may be embedded in one or more of the devices in the cell. In another configuration, the gate capacitance of each device within the SRAM bit cell may be adjusted to achieve high SRAM yield. For instance, a thick gate oxide may be used, phosphorous pre-doping may be used or fluorine pre-doping may be used in one or more of the devices within the cell.
    Type: Application
    Filed: August 23, 2010
    Publication date: December 16, 2010
    Applicant: TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
    Inventor: Katsura Miyashita
  • Patent number: 7820492
    Abstract: An electrical fuse (eFuse) has a gate prepared from a conductive or partially conductive material such as polysilicon, a semiconductor substrate having a pipe region in proximity to the gate, and first and second electrode regions adjacent the pipe region. A metal silicide layer is provided on the semiconductor substrate adjacent the pipe region. When a programming voltage is applied, the metal silicide undergoes a thermally induced phase transition in the pipe region. The eFuse has improved reliability and can be programmed with relatively low voltages.
    Type: Grant
    Filed: May 25, 2007
    Date of Patent: October 26, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsura Miyashita, Yoshiaki Toyoshima
  • Publication number: 20100117163
    Abstract: A semiconductor device according to one embodiment includes: a gate electrode formed on a semiconductor substrate via a gate insulating film; first and second spacers respectively formed on two side faces of the gate electrode; a gate sidewall formed on a side face of the first spacer; a channel region formed in the semiconductor substrate under the gate insulating film; first and second impurity diffused layers respectively formed on the first spacer side and the second spacer side of the channel region, the first impurity diffused layer including a first extension region in the gate electrode side thereon, the second impurity diffused layer including a second extension region in the gate electrode side thereon; a first silicide layer formed on the first impurity diffused layer; and a second silicide layer formed on the second impurity diffused layer, the channel region being closer to the second silicide layer than the first silicide layer.
    Type: Application
    Filed: September 15, 2009
    Publication date: May 13, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Katsura Miyashita
  • Patent number: 7652335
    Abstract: A semiconductor device having a silicon layer, a transistor having an electrical connection region in the silicon layer; and a conductive plug formed on and in electrical contact with the electrical connection region, the plug having side walls that taper inward away from the silicon layer.
    Type: Grant
    Filed: October 17, 2007
    Date of Patent: January 26, 2010
    Assignee: Toshiba America Electronics Components, Inc.
    Inventor: Katsura Miyashita
  • Patent number: 7638432
    Abstract: The present invention provides a semiconductor device, comprising a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, and source-drain diffusion layer formed within the semiconductor substrate in the vicinity of the gate electrode. A silicide film is formed on each of the gate electrode and the source-drain diffusion layer. The silicide film positioned on the gate electrode is thicker than the silicide film positioned on the source-drain diffusion layer. The present invention also provides a method of manufacturing a semiconductor device, in which a gate electrode is formed on a gate insulating film covering a semiconductor substrate, followed by forming a source-drain diffusion layer within the semiconductor substrate.
    Type: Grant
    Filed: April 23, 2007
    Date of Patent: December 29, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsura Miyashita, Hisao Yoshimura, Mariko Takagi
  • Publication number: 20090230432
    Abstract: A hybrid substrate circuit on a common substrate is disclosed. A first circuit formed in a first semiconductor material is isolated via a buried oxide layer from a second circuit formed in a second semiconductor material. The first and second circuits may include CMOS, HEMTs, P-HEMTs, HBTs, radio frequency circuits, MESFETs, and various pFETs and nFETs.
    Type: Application
    Filed: March 9, 2009
    Publication date: September 17, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Katsura Miyashita
  • Publication number: 20090224290
    Abstract: A system and method for ion implantation during semiconductor fabrication. An integrated circuit may be designed with proximately located one-directional transistor gates. A two-way halo ion implantation is performed perpendicularly to the transistor gates in order to embed the dopant into the silicon body on the surface of the semiconductor wafer. The two-way halo both reduces the channeling effect by allowing ion implantation beneath the transistor gate, and reduces the halo shadowing effect resulting from halo implanting which is done parallel to the transistor gates.
    Type: Application
    Filed: March 3, 2009
    Publication date: September 10, 2009
    Inventor: Katsura Miyashita
  • Publication number: 20090224263
    Abstract: A structure for generating stress in a field effect transistor is described. Combinations of materials are described that when juxtaposed provide one of tensile or compressive stress to a channel region. In one or more aspects, tensile stress is provided to a channel region by materials having similar but different lattice constants.
    Type: Application
    Filed: March 6, 2008
    Publication date: September 10, 2009
    Applicant: TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
    Inventor: Katsura Miyashita
  • Publication number: 20090189227
    Abstract: A SRAM bit cell and an associated method of producing the SRAM bit cell with improved performance and stability is provided. In one configuration, channel mobility of the transistors within the SRAM bit cell may be adjusted to provide improved stability. In order to adjust the channel mobility, a stress memorization technique may be used, a wide spacer may be used, germanium may be implanted on tensile stress silicon nitride, a compressive liner may be used or silicon germanium may be embedded in one or more of the devices in the cell. In another configuration, the gate capacitance of each device within the SRAM bit cell may be adjusted to achieve high SRAM yield. For instance, a thick gate oxide may be used, phosphorous pre-doping may be used or fluorine pre-doping may be used in one or more of the devices within the cell.
    Type: Application
    Filed: January 25, 2008
    Publication date: July 30, 2009
    Applicant: TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
    Inventor: Katsura Miyashita
  • Publication number: 20090189198
    Abstract: An SRAM bit cell structure that can be produced in small sizes while maintaining performance is presented. In one configuration, an SRAM bit cell includes driver field effect transistors that are p-type field effect transistors, load field effect transistors that are n-type field effect transistors and transfer gates that are p-type field effect transistors. Each field effect transistor may be arranged on a substrate that will enhance performance. In one arrangement, the p-type field effect transistors may be arranged on a silicon (110) substrate to enhance hole mobility while the n-type field effect transistors may be arranged on a silicon on insulator (100) substrate to enhance electron mobility. In another arrangement, the load n-type field effect transistor may be arranged on the same silicon (110) substrate as the other field effect transistors in the cell.
    Type: Application
    Filed: January 25, 2008
    Publication date: July 30, 2009
    Applicant: TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
    Inventor: Katsura Miyashita
  • Publication number: 20090101943
    Abstract: A semiconductor device having a silicon layer, a transistor having an electrical connection region in the silicon layer; and a conductive plug formed on and in electrical contact with the electrical connection region, the plug having side walls that taper inward away from the silicon layer.
    Type: Application
    Filed: October 17, 2007
    Publication date: April 23, 2009
    Applicant: Toshiba America Electronic Components, Inc.
    Inventor: Katsura Miyashita
  • Publication number: 20080290456
    Abstract: An electrical fuse (eFuse) has a gate prepared from a conductive or partially conductive material such as polysilicon, a semiconductor substrate having a pipe region in proximity to the gate, and first and second electrode regions adjacent the pipe region. A metal silicide layer is provided on the semiconductor substrate adjacent the pipe region. When a programming voltage is applied, the metal silicide undergoes a thermally induced phase transition in the pipe region. The eFuse has improved reliability and can be programmed with relatively low voltages.
    Type: Application
    Filed: May 25, 2007
    Publication date: November 27, 2008
    Applicant: Toshiba America Electronic Components, Inc.
    Inventors: Katsura Miyashita, Yoshiaki Toyoshima
  • Publication number: 20080157215
    Abstract: Structures for reducing or even preventing the diffusion from an NFET side of a gate to a PFET side of the gate in a semiconductor device are disclosed, as well as manufacturing methods thereof. A diffusion barrier is formed in the shared gate at the N/P boundary between the NFET and the PFET. The diffusion barrier is doped with one or more types of ions, such as, but not limited to, oxygen, nitrogen, fluorine, silicon, germanium, or xenon ions. By using a diffusion barrier as disclosed herein, the diffusion of ions through a common gate from the NFET side to the PFET side in a CMOS technology semiconductor device node may be significantly reduced or even prevented altogether. This may further result in relatively higher performance of the NFET/PFET pair.
    Type: Application
    Filed: December 28, 2006
    Publication date: July 3, 2008
    Applicant: TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
    Inventor: Katsura Miyashita
  • Publication number: 20080067629
    Abstract: An electrical fuse has a substrate and a resistor. The resistor has a first area and a second area embedded in the first area. The first area is formed of a first material and the second area is formed of a second material having a lower thermal stability than that of the first material. Because of the different thermal stabilities, the second area is more likely to rupture when a programming voltage is applied. The eFuse provides increased reliability and enables lower programming voltages to be used.
    Type: Application
    Filed: August 17, 2006
    Publication date: March 20, 2008
    Applicant: TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
    Inventor: Katsura Miyashita
  • Publication number: 20070194382
    Abstract: The present invention provides a semiconductor device, comprising a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, and source-drain diffusion layer formed within the semiconductor substrate in the vicinity of the gate electrode. A silicide film is formed on each of the gate electrode and the source-drain diffusion layer. The silicide film positioned on the gate electrode is thicker than the silicide film positioned on the source-drain diffusion layer. The present invention also provides a method of manufacturing a semiconductor device, in which a gate electrode is formed on a gate insulating film covering a semiconductor substrate, followed by forming a source-drain diffusion layer within the semiconductor substrate.
    Type: Application
    Filed: April 23, 2007
    Publication date: August 23, 2007
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Katsura Miyashita, Hisao Yoshimura, Mariko Takagi
  • Patent number: 7220672
    Abstract: The invention provides a semiconductor device, and a manufacturing method, comprising a semiconductor substrate, a gate insulating film, a gate electrode, and a source-drain diffusion layer. A silicide film is formed on the gate electrode and the source-drain diffusion layer. The silicide film is thicker on the gate electrode than on the source-drain diffusion layer. The manufacturing method comprises forming a gate electrode on a gate insulating film, followed by forming a source-drain diffusion layer. Then, atoms inhibiting a silicidation are selectively introduced into the source-drain diffusion layer, and a high melting point metal film is formed on the gate electrode and the source-drain diffusion layer. The high melting point metal film is converted into silicide films selectively on the gate electrode and the source-drain diffusion layer.
    Type: Grant
    Filed: February 8, 2005
    Date of Patent: May 22, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsura Miyashita, Hisao Yoshimura, Mariko Takagi
  • Publication number: 20050186748
    Abstract: A method of manufacturing a semiconductor device including a plurality of MIS transistors formed on a semiconductor substrate, includes forming a plurality of gate electrodes associated with the MIS transistors on the semiconductor substrate, with a plurality of gate insulating films interposed between the gate electrodes and the semiconductor substrate, respectively, and successively forming a plurality of impurity diffusion regions for LDD regions in the semiconductor substrate, at decreasing junction depths, respectively, by using lithography and ion implantation, such that each of the impurity diffusion regions being provided on both sides of a respective one of the gate electrodes.
    Type: Application
    Filed: January 21, 2005
    Publication date: August 25, 2005
    Inventors: Ryoji Hasumi, Katsura Miyashita