Abstract: A semiconductor device includes: a semiconductor part including a first semiconductor layer and a second semiconductor layer in contact with the first semiconductor layer; a first electrode electrically connected to the first semiconductor layer on a front surface side or a back surface side of the semiconductor part; a second electrode electrically connected to the second semiconductor layer on the front surface side of the semiconductor part; a gate electrode; an interlayer insulating film electrically insulating the gate electrode and the second electrode on the front surface side of the semiconductor part; and a third semiconductor layer having: a first region in contact with the second semiconductor layer and the second electrode on the front surface side of the semiconductor part; and a second region provided between the interlayer insulating film and the second electrode in a second direction perpendicular to a first direction.

Abstract: A semiconductor device includes a first electrode, a second electrode located on the first electrode, a semiconductor part located between the first electrode and the second electrode, a first interconnect located between the semiconductor part and the second electrode, a third electrode located in the semiconductor part and separated from the semiconductor part, a fourth electrode located lower than the third electrode in the semiconductor part, a first plug connecting the second electrode to the fourth electrode, and a second plug. The third electrode includes a ring portion, and an extension portion extending from the ring portion into an interior of the ring portion. The fourth electrode is located in the interior of the ring portion in a plane perpendicular to a vertical direction. The fourth electrode is separated from the semiconductor part. The second plug connects the first interconnect to the extension portion.

Abstract: According to one embodiment, a semiconductor chip includes a first electrode, a semiconductor layer, a second electrode, a third electrode, and a metallic layer. The semiconductor layer includes a first portion, a second portion, and a third portion that is located between the first portion and the second portion. The semiconductor layer is provided on a first side of the first electrode in a first direction. The second electrode is over the first portion in the first direction. The third electrode is over the second portion in the first direction. The metallic layer is provided on a second side of the first electrode and is under the third portion in the first direction.

Abstract: A SRAM bit cell and an associated method of producing the SRAM bit cell with improved performance and stability is provided. In one configuration, channel mobility of the transistors within the SRAM bit cell may be adjusted to provide improved stability. In order to adjust the channel mobility, a stress memorization technique may be used, a wide spacer may be used, germanium may be implanted on tensile stress silicon nitride, a compressive liner may be used or silicon germanium may be embedded in one or more of the devices in the cell. In another configuration, the gate capacitance of each device within the SRAM bit cell may be adjusted to achieve high SRAM yield. For instance, a thick gate oxide may be used, phosphorous pre-doping may be used or fluorine pre-doping may be used in one or more of the devices within the cell.

Abstract: A hybrid substrate circuit on a common substrate is disclosed. A first circuit formed in a first semiconductor material is isolated via a buried oxide layer from a second circuit formed in a second semiconductor material. The first and second circuits may include CMOS, HEMTs, P-HEMTs, HBTs, radio frequency circuits, MESFETs, and various pFETs and nFETs.

Abstract: A system and method for ion implantation during semiconductor fabrication. An integrated circuit may be designed with proximately located one-directional transistor gates. A two-way halo ion implantation is performed perpendicularly to the transistor gates in order to embed the dopant into the silicon body on the surface of the semiconductor wafer. The two-way halo both reduces the channeling effect by allowing ion implantation beneath the transistor gate, and reduces the halo shadowing effect resulting from halo implanting which is done parallel to the transistor gates.

Abstract: A SRAM bit cell and an associated method of producing the SRAM bit cell with improved performance and stability is provided. In one configuration, channel mobility of the transistors within the SRAM bit cell may be adjusted to provide improved stability. In order to adjust the channel mobility, a stress memorization technique may be used, a wide spacer may be used, germanium may be implanted on tensile stress silicon nitride, a compressive liner may be used or silicon germanium may be embedded in one or more of the devices in the cell. In another configuration, the gate capacitance of each device within the SRAM bit cell may be adjusted to achieve high SRAM yield. For instance, a thick gate oxide may be used, phosphorous pre-doping may be used or fluorine pre-doping may be used in one or more of the devices within the cell.

Abstract: An electrical fuse (eFuse) has a gate prepared from a conductive or partially conductive material such as polysilicon, a semiconductor substrate having a pipe region in proximity to the gate, and first and second electrode regions adjacent the pipe region. A metal silicide layer is provided on the semiconductor substrate adjacent the pipe region. When a programming voltage is applied, the metal silicide undergoes a thermally induced phase transition in the pipe region. The eFuse has improved reliability and can be programmed with relatively low voltages.

Abstract: A semiconductor device according to one embodiment includes: a gate electrode formed on a semiconductor substrate via a gate insulating film; first and second spacers respectively formed on two side faces of the gate electrode; a gate sidewall formed on a side face of the first spacer; a channel region formed in the semiconductor substrate under the gate insulating film; first and second impurity diffused layers respectively formed on the first spacer side and the second spacer side of the channel region, the first impurity diffused layer including a first extension region in the gate electrode side thereon, the second impurity diffused layer including a second extension region in the gate electrode side thereon; a first silicide layer formed on the first impurity diffused layer; and a second silicide layer formed on the second impurity diffused layer, the channel region being closer to the second silicide layer than the first silicide layer.

Abstract: A semiconductor device having a silicon layer, a transistor having an electrical connection region in the silicon layer; and a conductive plug formed on and in electrical contact with the electrical connection region, the plug having side walls that taper inward away from the silicon layer.

Abstract: The present invention provides a semiconductor device, comprising a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, and source-drain diffusion layer formed within the semiconductor substrate in the vicinity of the gate electrode. A silicide film is formed on each of the gate electrode and the source-drain diffusion layer. The silicide film positioned on the gate electrode is thicker than the silicide film positioned on the source-drain diffusion layer. The present invention also provides a method of manufacturing a semiconductor device, in which a gate electrode is formed on a gate insulating film covering a semiconductor substrate, followed by forming a source-drain diffusion layer within the semiconductor substrate.

Abstract: A hybrid substrate circuit on a common substrate is disclosed. A first circuit formed in a first semiconductor material is isolated via a buried oxide layer from a second circuit formed in a second semiconductor material. The first and second circuits may include CMOS, HEMTs, P-HEMTs, HBTs, radio frequency circuits, MESFETs, and various pFETs and nFETs.

Abstract: A system and method for ion implantation during semiconductor fabrication. An integrated circuit may be designed with proximately located one-directional transistor gates. A two-way halo ion implantation is performed perpendicularly to the transistor gates in order to embed the dopant into the silicon body on the surface of the semiconductor wafer. The two-way halo both reduces the channeling effect by allowing ion implantation beneath the transistor gate, and reduces the halo shadowing effect resulting from halo implanting which is done parallel to the transistor gates.

Abstract: A structure for generating stress in a field effect transistor is described. Combinations of materials are described that when juxtaposed provide one of tensile or compressive stress to a channel region. In one or more aspects, tensile stress is provided to a channel region by materials having similar but different lattice constants.

Abstract: An SRAM bit cell structure that can be produced in small sizes while maintaining performance is presented. In one configuration, an SRAM bit cell includes driver field effect transistors that are p-type field effect transistors, load field effect transistors that are n-type field effect transistors and transfer gates that are p-type field effect transistors. Each field effect transistor may be arranged on a substrate that will enhance performance. In one arrangement, the p-type field effect transistors may be arranged on a silicon (110) substrate to enhance hole mobility while the n-type field effect transistors may be arranged on a silicon on insulator (100) substrate to enhance electron mobility. In another arrangement, the load n-type field effect transistor may be arranged on the same silicon (110) substrate as the other field effect transistors in the cell.

Abstract: A SRAM bit cell and an associated method of producing the SRAM bit cell with improved performance and stability is provided. In one configuration, channel mobility of the transistors within the SRAM bit cell may be adjusted to provide improved stability. In order to adjust the channel mobility, a stress memorization technique may be used, a wide spacer may be used, germanium may be implanted on tensile stress silicon nitride, a compressive liner may be used or silicon germanium may be embedded in one or more of the devices in the cell. In another configuration, the gate capacitance of each device within the SRAM bit cell may be adjusted to achieve high SRAM yield. For instance, a thick gate oxide may be used, phosphorous pre-doping may be used or fluorine pre-doping may be used in one or more of the devices within the cell.

Abstract: A semiconductor device having a silicon layer, a transistor having an electrical connection region in the silicon layer; and a conductive plug formed on and in electrical contact with the electrical connection region, the plug having side walls that taper inward away from the silicon layer.

Abstract: An electrical fuse (eFuse) has a gate prepared from a conductive or partially conductive material such as polysilicon, a semiconductor substrate having a pipe region in proximity to the gate, and first and second electrode regions adjacent the pipe region. A metal silicide layer is provided on the semiconductor substrate adjacent the pipe region. When a programming voltage is applied, the metal silicide undergoes a thermally induced phase transition in the pipe region. The eFuse has improved reliability and can be programmed with relatively low voltages.

Abstract: Structures for reducing or even preventing the diffusion from an NFET side of a gate to a PFET side of the gate in a semiconductor device are disclosed, as well as manufacturing methods thereof. A diffusion barrier is formed in the shared gate at the N/P boundary between the NFET and the PFET. The diffusion barrier is doped with one or more types of ions, such as, but not limited to, oxygen, nitrogen, fluorine, silicon, germanium, or xenon ions. By using a diffusion barrier as disclosed herein, the diffusion of ions through a common gate from the NFET side to the PFET side in a CMOS technology semiconductor device node may be significantly reduced or even prevented altogether. This may further result in relatively higher performance of the NFET/PFET pair.

Abstract: An electrical fuse has a substrate and a resistor. The resistor has a first area and a second area embedded in the first area. The first area is formed of a first material and the second area is formed of a second material having a lower thermal stability than that of the first material. Because of the different thermal stabilities, the second area is more likely to rupture when a programming voltage is applied. The eFuse provides increased reliability and enables lower programming voltages to be used.