Abstract: A static RAM having first word lines each defined by extended gate electrodes of MISFETs constituting memory cells, and second word lines which are separate from the first word lines. The RAM further has a wiring for supplying a fixed potential such as a ground potential to the memory cells, the wiring being formed from the same layer as that for forming the second word lines.

Abstract: Information read out from a memory cell of a static type semiconductor memory is subjected to multi-stage sense amplification in an initial stage sense amplifier, a post-stage sense amplifier and a main amplifier and then transmitted to the input of an output buffer circuit. Since an equalizing circuit is connected to the complementary inputs of each stage of the multi-stage sense amplifier, an inverse information read operation can be executed at high speed. Initially, the initial stage sense amplifier, the post-stage sense amplifier and the main amplifier are controlled to operate in high amplification gain conditions so as to execute high speed sense amplification and thereafter controlled to operate in such low power consumption conditions that the read-out information output obtained by the high speed sense amplification will not disappear.

Abstract: In a constant current-constant voltage circuit disclosed herein, gates of MOSFETs Q.sub.1 and Q.sub.2 are connected together, and the gate of the MOSFET Q.sub.1 is connected to the drain thereof. Further, the source of the MOSFET Q.sub.1 is connected to ground potential GND whereas the source of the MOSFET Q.sub.2 is connected to the drain of a MOSFET Q.sub.3 having a gate connected to power supply voltage V.sub.DD and a source connected to the ground voltage GND. A current mirror circuit including Q.sub.4 and Q.sub.5 has an input and an output respectively connected to the drain of the second MOSFET Q.sub.2 and the drain of the first MOSFET Q.sub.1. A first coefficient (W.sub.3 L.sub.2 /L.sub.3 W.sub.2) depending upon channel lengths (L.sub.2, L.sub.3) and channel widths (W.sub.2, W.sub.3) of the MOSFETs Q.sub.2 and Q.sub.3 is set at a value not larger than a predetermined value. Therefore, the MOSFET Q.sub.3 operates in a linear region as high resistance, and the MOSFETs Q.sub.1 and Q.sub.

Abstract: A method and apparatus for quickly masking defective memory elements with substitute memory elements includes first and second memory blocks. The first memory block includes a first memory array and a second spare memory array. The second memory block includes a second memory array and a first spare memory array. A first word from the first memory array is selected concurrently with a first substitute word from the first spare memory. An address signal is decoded and then compared with data representative of a defective word. In the event it is determined, as a result of this comparison, that the first word is defective, the first substitute word is then communicated to a common data bus. Alternatively, the first word is communicated to the common data bus.

Abstract: A static RAM having first word lines each defined by extended gate electrodes of MISFETs constituting memory cells, and second word lines which are separate from the first word lines. The RAM has a wiring for supplying a fixed potential such as a ground potential to the memory cells, the wiring being formed from the same layer as that for forming the second word lines.

Abstract: Information read out from a memory cell of a static type semiconductor memory is subjected to multi-stage sense amplification in an initial stage sense amplifier, a post-stage snese amplifier and a main amplifier and then transmitted to the input of an output buffer circuit. Since an equalizing circuit is connected to the complementary inputs of each stage of the multi-stage sense amplifier, an inverse information read operation can be executed at high speed. Initially, the initial stage sense amplifier, the post-stage sense amplifier and the main amplifier are controlled to operate in high amplification gain conditions so as to execute high speed sense amplification and thereafter controlled to operate in such low power consumption conditions that the read-out information output obtained by the high speed sense amplification will not disappear.