Patents by Inventor Katsushige Matsubara

Katsushige Matsubara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10782886
    Abstract: To provide a semiconductor device which suppresses a delay in processing. The semiconductor device is equipped with a plurality of read units which read data stored across a plurality of banks in a memory having the banks, and an access method managing section which, when one of the read units reads the data, determines a read start bank number being a bank number to start reading according to operation situations of the read units excepting the one read unit, and instructs the determined read start bank number to the one read unit.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: September 22, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Nhat Van Huynh, Seiji Mochizuki, Katsushige Matsubara, Toshiyuki Kaya
  • Patent number: 10725512
    Abstract: A CPU needs to perform reset operation when a secondary arithmetic processing unit controlled by the CPU controls a signal processing circuit. CPU A controls module A. CPU B controls module B. Module A and module B control a signal processing circuit. CPU A and CPU B issue a reset request to the signal processing circuit. The signal processing circuit performs a reset process based on the reset request accepted from the CPU and a control origin identification signal that identifies a CPU as an origin of controlling the module having started a signal processing section.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: July 28, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hiroshi Ueda, Ryoji Hashimoto, Taku Maekawa, Katsushige Matsubara, Keisuke Matsumoto
  • Publication number: 20200233471
    Abstract: A CPU needs to perform reset operation when a secondary arithmetic processing unit controlled by the CPU controls a signal processing circuit. CPU A controls module A. CPU B controls module B. Module A and module B control a signal processing circuit. CPU A and CPU B issue a reset request to the signal processing circuit. The signal processing circuit performs a reset process based on the reset request accepted from the CPU and a control origin identification signal that identifies a CPU as an origin of controlling the module having started a signal processing section.
    Type: Application
    Filed: April 7, 2020
    Publication date: July 23, 2020
    Inventors: Hiroshi UEDA, Ryoji HASHIMOTO, Taku MAEKAWA, Katsushige MATSUBARA, Keisuke MATSUMOTO
  • Patent number: 10719440
    Abstract: Regarding association between an area where compressed data is stored and an area where auxiliary information required to access the compressed data is stored, it is necessary to manage the association by software for each processing unit, so that the processing becomes complicated. A management unit memory area including a compressed data storage area and an auxiliary information storage area including auxiliary information are defined on a memory space. By calculating an auxiliary information address from an address indicating a location on a memory where a management unit memory space is set, an address of the auxiliary information storage area, and an address of the compressed data, the compressed data and the auxiliary information are associated with each other and the auxiliary information is read.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: July 21, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Keisuke Matsumoto, Seiji Mochizuki, Hiroshi Ueda, Katsushige Matsubara
  • Publication number: 20200228842
    Abstract: Provided is a data processing device that reduces the amount of memory access in a case where data and an error control code are to be stored in a memory. The processing device includes a data compression section, a code generation section, a binding section, and a transfer section. The data compression section generates second data by performing a predetermined compression process on first data that is to be stored in a memory and of a predetermined data length. The code generation section generates an error control code for the first data or the second data. The binding section generates third data by binding the second data generated by the data compression section to the error control code generated by the code generation section. The transfer section transfers the third data generated by the binding section to the memory in units of the predetermined data length.
    Type: Application
    Filed: March 30, 2020
    Publication date: July 16, 2020
    Inventors: Katsushige MATSUBARA, Seiji MOCHIZUKI, Keisuke MATSUMOTO
  • Publication number: 20200201552
    Abstract: A semiconductor device for achieving consistency of data is provided. The process performed by the semiconductor device includes a step of compressing data to generate compression information representing compressed data and the amount of information, a step of accessing management data for controlling access to a memory area, a step of permitting writing to a memory area in units of a predetermined data size based on the fact that the management data indicates that the accessed area is not exclusively allocated to another compression/expansion module, a step of writing data to update management data, a step of permitting reading from the area in units of the data size based on the fact that the management data indicates that the accessed area is not exclusively owned to another compression/expansion module, and a step of reading the compressed data and the compressed information from the area in units of the data size.
    Type: Application
    Filed: November 14, 2019
    Publication date: June 25, 2020
    Inventors: Katsushige MATSUBARA, Seiji MOCHIZUKI
  • Patent number: 10645420
    Abstract: Provided is a data processing device that reduces the amount of memory access in a case where data and an error control code are to be stored in a memory. The processing device includes a data compression section, a code generation section, a binding section, and a transfer section. The data compression section generates second data by performing a predetermined compression process on first data that is to be stored in a memory and of a predetermined data length. The code generation section generates an error control code for the first data or the second data. The binding section generates third data by binding the second data generated by the data compression section to the error control code generated by the code generation section. The transfer section transfers the third data generated by the binding section to the memory in units of the predetermined data length.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: May 5, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Katsushige Matsubara, Seiji Mochizuki, Keisuke Matsumoto
  • Patent number: 10642768
    Abstract: In a semiconductor device, a load of CPU required for arbitration when using a shared resource is reduced. The semiconductor device includes a CPU section and a hardware IP. In the CPU section, software modules are executed. The hardware IP includes a storage unit, an arbitration unit, and a calculation unit. The storage unit includes control receiving units that receive operation requests transmitted by the software modules, respectively. The calculation unit performs processing based on an operation request transmitted from the control receiving units. The arbitration unit controls information transmission between the control receiving units and the calculation unit so that the calculation unit receives only an operation request from any one of the control receiving units.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: May 5, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Masaru Hase, Tetsuji Tsuda, Naohiro Nishikawa, Yuki Inoue, Seiji Mochizuki, Katsushige Matsubara, Ren Imaoka
  • Patent number: 10497149
    Abstract: An image processing apparatus according to one embodiment determines target resolutions of a plurality of source images based on a first horizontal direction size and a first vertical direction size which are a horizontal direction size and a vertical direction size of a backlight control unit of a first display, and a second horizontal direction size and a second vertical direction size which are a horizontal direction size and a vertical direction size of a backlight control unit of a second display, and converts the resolution of each of a plurality of source images such that the resolution of each of a plurality of source images becomes the target resolution.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: December 3, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Ryuichi Igarashi, Seiji Mochizuki, Katsushige Matsubara, Toshiyuki Kaya
  • Patent number: 10459646
    Abstract: Disclosed is a semiconductor device capable of performing compression and decompression with increased appropriateness. The semiconductor device includes a computing module and a memory control module. The computing module includes a computing unit and a compression circuit. The computing unit performs arithmetic processing. The compression circuit compresses data indicative of the result of arithmetic processing. The memory control module includes an access circuit and a decompression circuit. The access circuit writes compressed data into a memory and reads written data from the memory. The decompression circuit decompresses data read from the memory and outputs the decompressed data to the computing module.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: October 29, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Katsushige Matsubara, Seiji Mochizuki, Ryoji Hashimoto, Toshiyuki Kaya, Kimihiko Nakazawa, Takahiro Irita, Tetsuji Tsuda
  • Patent number: 10461956
    Abstract: A semiconductor device includes a plurality of IP cores, a plurality of storage devices, a configuration information acquiring unit that acquires configuration information for specifying a timing when the IP core accesses the storage device, and an allocation determining unit that determines the storage device allocated to the IP core. The configuration information acquiring unit acquires configuration information regarding a first IP core and configuration information regarding a second IP core. The allocation determining unit determines, based on the configuration information, whether an access timing by the first IP core is the same as an access timing by the second IP core, and when it is determined that the access timings are the same, determines allocation in such a way that the storage device allocated to the first IP core becomes different from the storage device allocated to the second IP core.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: October 29, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tetsuji Tsuda, Masaru Hase, Yuki Inoue, Katsushige Matsubara
  • Patent number: 10452587
    Abstract: A plurality of transfer modules (402-0 to 402-M) that transfer data between processing units are provided so as to respectively correspond to a plurality of processing units (401-0 to 401-M). First ring buses (403-0 to 403-M) connect, for each of the processing units (401-0 to 401-M), subunits within a corresponding processing unit and the transfer module corresponding to the processing unit so that they form a ring shape. The plurality of transfer modules (402-0 to 402-M) are connected so that they form a ring shape by a second ring bus (404).
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: October 22, 2019
    Assignee: RENESAS ELECTRONICS COPRORATION
    Inventors: Hiroshi Ueda, Seiji Mochizuki, Toshiyuki Kaya, Kenichi Iwata, Katsushige Matsubara
  • Patent number: 10419753
    Abstract: A display area can be smoothly moved. A semiconductor device sequentially receives a plurality of whole images, each of which includes a plurality of small screen images and which are temporally continuous and form a moving image, and decodes a received whole image. Here, the semiconductor device includes a reception unit that receives the whole image including the small screen images, a determination unit that determines a decoding area which includes a small screen image to be decoded and which is included in the whole image, and a decoding unit that decodes the small screen image in the decoding area which is determined by the determination unit and which is included in the whole image. The determination unit determines a new decoding area when a small screen image of intra frame appears in the decoding area.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: September 17, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kazushi Akie, Seiji Mochizuki, Toshiyuki Kaya, Katsushige Matsubara, Hiroshi Ueda, Ren Imaoka, Ryoji Hashimoto
  • Patent number: 10362306
    Abstract: Included are an encoding section, a decoding section, and an image recognition section. The encoding section performs an encoding process for a video signal to be input based on a calculated encoding mode, and transmits an encoded stream. The decoding section performs a decoding process for the received encoded stream, and outputs a decoded image. The image recognition section performs an image recognition process for the decoded image. The encoding section adjusts the encoding mode based on recognition accuracy information representing the certainty of a recognition result in the image recognition section.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: July 23, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tetsuya Shibayama, Seiji Mochizuki, Katsushige Matsubara, Kenichi Iwata
  • Patent number: 10349072
    Abstract: An in-vehicle system includes a camera having an encoder encoding video obtained by the camera, an image processing apparatus which receives the encoded video from the camera, and an image recognition processing circuit performing image recognition on decoded video data from the image processing apparatus. The image processing apparatus includes a codec processing circuit which decodes the encoded video, a plurality of image processing circuits which execute tasks in parallel, an estimating circuit which estimates estimation time in which a process of the task is completed in each of the image processing circuit on the basis of the number of access times to a bus which is obtained on the basis of a parameter of decoding used in the codec processing circuit, and a scheduling circuit which schedules tasks to be executed by the plurality of image processing circuit on the basis of the estimation time.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: July 9, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Katsushige Matsubara, Takayuki Matsumi, Seiji Mochizuki, Kenichi Iwata, Toshiyuki Kaya
  • Patent number: 10334262
    Abstract: The present invention is directed to reduce deterioration in parallel processing capability. In a moving-picture decoding processing apparatus, information of a first plurality of frames and a second plurality of frames is supplied from a decoding control unit to first and second decoding processing units. For decoding the information from an intermediate point to an end point of a second preceding frame by the second decoding unit in a third period, use of a result of the process of the first decoding processing unit in the third period is inhibited, and use of a result of the process of a first preceding frame by the first decoding processing unit in a second period is permitted by an end signal.
    Type: Grant
    Filed: October 20, 2014
    Date of Patent: June 25, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Katsushige Matsubara, Seiji Mochizuki, Toshiyuki Kaya, Tetsuya Shibayama
  • Publication number: 20190171596
    Abstract: In a semiconductor device, a load of CPU required for arbitration when using a shared resource is reduced. The semiconductor device includes a CPU section and a hardware IP. In the CPU section, software modules are executed. The hardware IP includes a storage unit, an arbitration unit, and a calculation unit. The storage unit includes control receiving units that receive operation requests transmitted by the software modules, respectively. The calculation unit performs processing based on an operation request transmitted from the control receiving units. The arbitration unit controls information transmission between the control receiving units and the calculation unit so that the calculation unit receives only an operation request from any one of the control receiving units.
    Type: Application
    Filed: January 22, 2019
    Publication date: June 6, 2019
    Applicant: Renesas Electronics Corporation
    Inventors: Masaru HASE, Tetsuji Tsuda, Naohiro Nishikawa, Yuki Inoue, Seiji Mochizuki, Katsushige Matsubara, Ren Imaoka
  • Publication number: 20190146683
    Abstract: To provide a semiconductor device which suppresses a delay in processing. The semiconductor device is equipped with a plurality of read units which read data stored across a plurality of banks in a memory having the banks, and an access method managing section which, when one of the read units reads the data, determines a read start bank number being a bank number to start reading according to operation situations of the read units excepting the one read unit, and instructs the determined read start bank number to the one read unit.
    Type: Application
    Filed: September 11, 2018
    Publication date: May 16, 2019
    Inventors: Nhat Van HUYNH, Seiji MOCHIZUKI, Katsushige MATSUBARA, Toshiyuki KAYA
  • Publication number: 20190132611
    Abstract: Provided is a data processing device that reduces the amount of memory access in a case where data and an error control code are to be stored in a memory. The processing device includes a data compression section, a code generation section, a binding section, and a transfer section. The data compression section generates second data by performing a predetermined compression process on first data that is to be stored in a memory and of a predetermined data length. The code generation section generates an error control code for the first data or the second data. The binding section generates third data by binding the second data generated by the data compression section to the error control code generated by the code generation section. The transfer section transfers the third data generated by the binding section to the memory in units of the predetermined data length.
    Type: Application
    Filed: September 10, 2018
    Publication date: May 2, 2019
    Inventors: Katsushige MATSUBARA, Seiji MOCHIZUKI, Keisuke MATSUMOTO
  • Publication number: 20190095338
    Abstract: Bus/memory bandwidth consumption caused by reading of auxiliary information not included in compressed data is reduced. A memory stores compressed data and auxiliary information used to read the compressed data. A semiconductor device includes a cache in which auxiliary information stored in the memory is stored, a control unit which, when a read request for reading compressed data stored in the memory is received, reads from the cache auxiliary information about the compressed data, if stored in the cache, or reads the auxiliary information about the compressed data, if not stored in the cache, from the memory and stores the auxiliary information about the compressed data in the cache, and which reads the compressed data from the memory using the auxiliary information about the compressed data, and an expansion unit to expand the compressed data read from the memory.
    Type: Application
    Filed: November 29, 2018
    Publication date: March 28, 2019
    Inventors: Katsushige MATSUBARA, Keisuke MATSUMOTO, Seiji MOCHIZUKI