Patents by Inventor Katsushige Matsubara
Katsushige Matsubara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11726864Abstract: In a data processing device comprising a memory controller controlling writing/reading of data to/from the memory, a processor requesting writing/reading of data, and an error detection module requesting writing/reading of data to/from the memory controller in accordance with a request from the processor, an error detection module calculates a first error detection code of the first data having a write request from the processor, reads the second data having a read request from the processor from the memory, calculates a second error detection code from the read data, compares the first error detection code and the second error detection code, and transmits the result of the comparison to the external module.Type: GrantFiled: March 17, 2020Date of Patent: August 15, 2023Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Katsushige Matsubara, Ryoji Hashimoto, Takahiro Irita, Kenichi Shimada, Tetsuya Shibayama
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Patent number: 11687261Abstract: A semiconductor device for achieving consistency of data is provided. The process performed by the semiconductor device includes a step of compressing data to generate compression information representing compressed data and the amount of information, a step of accessing management data for controlling access to a memory area, a step of permitting writing to a memory area in units of a predetermined data size based on the fact that the management data indicates that the accessed area is not exclusively allocated to another compression/expansion module, a step of writing data to update management data, a step of permitting reading from the area in units of the data size based on the fact that the management data indicates that the accessed area is not exclusively owned to another compression/expansion module, and a step of reading the compressed data and the compressed information from the area in units of the data size.Type: GrantFiled: November 3, 2021Date of Patent: June 27, 2023Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Katsushige Matsubara, Seiji Mochizuki
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Patent number: 11687357Abstract: In a virtualization system that includes a hypervisor that performs OSID management for linking a plurality of OSs with resources, a guest OS that receives an initial value from the hypervisor and sets a OSID for each resource, and a OSID manager that sets a OSID for each resource, a new OSID created by OSID generator in OSID manager after a certain period of time has elapsed after setting the initial value is set to the guest OS and the IP (resource), and is requested to be updated to a new OSID set by the update controller in OSID manager. This enables simultaneous updating of OSID of the guest operating system and the resources, thus achieving high robustness.Type: GrantFiled: October 6, 2020Date of Patent: June 27, 2023Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Tetsuya Shibayama, Nhat Van Huynh, Katsushige Matsubara, Seiji Mochizuki
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Publication number: 20230176883Abstract: According to one embodiment, a semiconductor device restricts an OS capable of using a functional block by an OS identifier written in an attribute register for restricting an accessible OS, and creates operation setting values of a first input unit, a second input unit, and a screen synthesis unit per OS to describe them in a setting value list stored in a shared memory, and each of the first input unit, second input unit, and screen synthesis unit has a mask circuit that refers to the OS identifier of the attribute register and in which write of the operation setting values into the setting register group of an own block is hampered, the operation setting values being described in the setting value list created by an OS other than the OS having a use authority for the own block.Type: ApplicationFiled: October 6, 2022Publication date: June 8, 2023Inventors: Ryuichi IGARASHI, Kenichi TAKEDA, Katsushige MATSUBARA, Tetsuya SHIBAYAMA
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Patent number: 11360529Abstract: A CPU needs to perform reset operation when a secondary arithmetic processing unit controlled by the CPU controls a signal processing circuit. CPU A controls module A. CPU B controls module B. Module A and module B control a signal processing circuit. CPU A and CPU B issue a reset request to the signal processing circuit. The signal processing circuit performs a reset process based on the reset request accepted from the CPU and a control origin identification signal that identifies a CPU as an origin of controlling the module having started a signal processing section.Type: GrantFiled: April 7, 2020Date of Patent: June 14, 2022Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Hiroshi Ueda, Ryoji Hashimoto, Taku Maekawa, Katsushige Matsubara, Keisuke Matsumoto
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Publication number: 20220057950Abstract: A semiconductor device for achieving consistency of data is provided. The process performed by the semiconductor device includes a step of compressing data to generate compression information representing compressed data and the amount of information, a step of accessing management data for controlling access to a memory area, a step of permitting writing to a memory area in units of a predetermined data size based on the fact that the management data indicates that the accessed area is not exclusively allocated to another compression/expansion module, a step of writing data to update management data, a step of permitting reading from the area in units of the data size based on the fact that the management data indicates that the accessed area is not exclusively owned to another compression/expansion module, and a step of reading the compressed data and the compressed information from the area in units of the data size.Type: ApplicationFiled: November 3, 2021Publication date: February 24, 2022Inventors: Katsushige MATSUBARA, Seiji MOCHIZUKI
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Patent number: 11194491Abstract: A semiconductor device for achieving consistency of data is provided. The process performed by the semiconductor device includes a step of compressing data to generate compression information representing compressed data and the amount of information, a step of accessing management data for controlling access to a memory area, a step of permitting writing to a memory area in units of a predetermined data size based on the fact that the management data indicates that the accessed area is not exclusively allocated to another compression/expansion module, a step of writing data to update management data, a step of permitting reading from the area in units of the data size based on the fact that the management data indicates that the accessed area is not exclusively owned to another compression/expansion module, and a step of reading the compressed data and the compressed information from the area in units of the data size.Type: GrantFiled: November 14, 2019Date of Patent: December 7, 2021Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Katsushige Matsubara, Seiji Mochizuki
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Patent number: 11190805Abstract: Provided is a data processing device that reduces the amount of memory access in a case where data and an error control code are to be stored in a memory. The processing device includes a data compression section, a code generation section, a binding section, and a transfer section. The data compression section generates second data by performing a predetermined compression process on first data that is to be stored in a memory and of a predetermined data length. The code generation section generates an error control code for the first data or the second data. The binding section generates third data by binding the second data generated by the data compression section to the error control code generated by the code generation section. The transfer section transfers the third data generated by the binding section to the memory in units of the predetermined data length.Type: GrantFiled: March 30, 2020Date of Patent: November 30, 2021Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Katsushige Matsubara, Seiji Mochizuki, Keisuke Matsumoto
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Publication number: 20210294691Abstract: In a data processing device comprising a memory controller controlling writing/reading of data to/from the memory, a processor requesting writing/reading of data, and an error detection module requesting writing/reading of data to/from the memory controller in accordance with a request from the processor, an error detection module calculates a first error detection code of the first data having a write request from the processor, reads the second data having a read request from the processor from the memory, calculates a second error detection code from the read data, compares the first error detection code and the second error detection code, and transmits the result of the comparison to the external module.Type: ApplicationFiled: March 17, 2020Publication date: September 23, 2021Inventors: Katsushige MATSUBARA, Ryoji HASHIMOTO, Takahiro IRITA, Kenichi SHIMADA, Tetsuya SHIBAYAMA
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Publication number: 20210132978Abstract: In a virtualization system that includes a hypervisor that performs OSID management for linking a plurality of OSs with resources, a guest OS that receives an initial value from the hypervisor and sets a OSID for each resource, and a OSID manager that sets a OSID for each resource, a new OSID created by OSID generator in OSID manager after a certain period of time has elapsed after setting the initial value is set to the guest OS and the IP (resource), and is requested to be updated to a new OSID set by the update controller in OSID manager. This enables simultaneous updating of OSID of the guest operating system and the resources, thus achieving high robustness.Type: ApplicationFiled: October 6, 2020Publication date: May 6, 2021Inventors: Tetsuya SHIBAYAMA, Nhat Van HUYNH, Katsushige MATSUBARA, Seiji MOCHIZUKI
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Patent number: 10782886Abstract: To provide a semiconductor device which suppresses a delay in processing. The semiconductor device is equipped with a plurality of read units which read data stored across a plurality of banks in a memory having the banks, and an access method managing section which, when one of the read units reads the data, determines a read start bank number being a bank number to start reading according to operation situations of the read units excepting the one read unit, and instructs the determined read start bank number to the one read unit.Type: GrantFiled: September 11, 2018Date of Patent: September 22, 2020Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Nhat Van Huynh, Seiji Mochizuki, Katsushige Matsubara, Toshiyuki Kaya
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Patent number: 10725512Abstract: A CPU needs to perform reset operation when a secondary arithmetic processing unit controlled by the CPU controls a signal processing circuit. CPU A controls module A. CPU B controls module B. Module A and module B control a signal processing circuit. CPU A and CPU B issue a reset request to the signal processing circuit. The signal processing circuit performs a reset process based on the reset request accepted from the CPU and a control origin identification signal that identifies a CPU as an origin of controlling the module having started a signal processing section.Type: GrantFiled: December 29, 2017Date of Patent: July 28, 2020Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Hiroshi Ueda, Ryoji Hashimoto, Taku Maekawa, Katsushige Matsubara, Keisuke Matsumoto
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Publication number: 20200233471Abstract: A CPU needs to perform reset operation when a secondary arithmetic processing unit controlled by the CPU controls a signal processing circuit. CPU A controls module A. CPU B controls module B. Module A and module B control a signal processing circuit. CPU A and CPU B issue a reset request to the signal processing circuit. The signal processing circuit performs a reset process based on the reset request accepted from the CPU and a control origin identification signal that identifies a CPU as an origin of controlling the module having started a signal processing section.Type: ApplicationFiled: April 7, 2020Publication date: July 23, 2020Inventors: Hiroshi UEDA, Ryoji HASHIMOTO, Taku MAEKAWA, Katsushige MATSUBARA, Keisuke MATSUMOTO
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Patent number: 10719440Abstract: Regarding association between an area where compressed data is stored and an area where auxiliary information required to access the compressed data is stored, it is necessary to manage the association by software for each processing unit, so that the processing becomes complicated. A management unit memory area including a compressed data storage area and an auxiliary information storage area including auxiliary information are defined on a memory space. By calculating an auxiliary information address from an address indicating a location on a memory where a management unit memory space is set, an address of the auxiliary information storage area, and an address of the compressed data, the compressed data and the auxiliary information are associated with each other and the auxiliary information is read.Type: GrantFiled: August 7, 2018Date of Patent: July 21, 2020Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Keisuke Matsumoto, Seiji Mochizuki, Hiroshi Ueda, Katsushige Matsubara
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Publication number: 20200228842Abstract: Provided is a data processing device that reduces the amount of memory access in a case where data and an error control code are to be stored in a memory. The processing device includes a data compression section, a code generation section, a binding section, and a transfer section. The data compression section generates second data by performing a predetermined compression process on first data that is to be stored in a memory and of a predetermined data length. The code generation section generates an error control code for the first data or the second data. The binding section generates third data by binding the second data generated by the data compression section to the error control code generated by the code generation section. The transfer section transfers the third data generated by the binding section to the memory in units of the predetermined data length.Type: ApplicationFiled: March 30, 2020Publication date: July 16, 2020Inventors: Katsushige MATSUBARA, Seiji MOCHIZUKI, Keisuke MATSUMOTO
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Publication number: 20200201552Abstract: A semiconductor device for achieving consistency of data is provided. The process performed by the semiconductor device includes a step of compressing data to generate compression information representing compressed data and the amount of information, a step of accessing management data for controlling access to a memory area, a step of permitting writing to a memory area in units of a predetermined data size based on the fact that the management data indicates that the accessed area is not exclusively allocated to another compression/expansion module, a step of writing data to update management data, a step of permitting reading from the area in units of the data size based on the fact that the management data indicates that the accessed area is not exclusively owned to another compression/expansion module, and a step of reading the compressed data and the compressed information from the area in units of the data size.Type: ApplicationFiled: November 14, 2019Publication date: June 25, 2020Inventors: Katsushige MATSUBARA, Seiji MOCHIZUKI
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Patent number: 10645420Abstract: Provided is a data processing device that reduces the amount of memory access in a case where data and an error control code are to be stored in a memory. The processing device includes a data compression section, a code generation section, a binding section, and a transfer section. The data compression section generates second data by performing a predetermined compression process on first data that is to be stored in a memory and of a predetermined data length. The code generation section generates an error control code for the first data or the second data. The binding section generates third data by binding the second data generated by the data compression section to the error control code generated by the code generation section. The transfer section transfers the third data generated by the binding section to the memory in units of the predetermined data length.Type: GrantFiled: September 10, 2018Date of Patent: May 5, 2020Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Katsushige Matsubara, Seiji Mochizuki, Keisuke Matsumoto
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Patent number: 10642768Abstract: In a semiconductor device, a load of CPU required for arbitration when using a shared resource is reduced. The semiconductor device includes a CPU section and a hardware IP. In the CPU section, software modules are executed. The hardware IP includes a storage unit, an arbitration unit, and a calculation unit. The storage unit includes control receiving units that receive operation requests transmitted by the software modules, respectively. The calculation unit performs processing based on an operation request transmitted from the control receiving units. The arbitration unit controls information transmission between the control receiving units and the calculation unit so that the calculation unit receives only an operation request from any one of the control receiving units.Type: GrantFiled: January 22, 2019Date of Patent: May 5, 2020Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Masaru Hase, Tetsuji Tsuda, Naohiro Nishikawa, Yuki Inoue, Seiji Mochizuki, Katsushige Matsubara, Ren Imaoka
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Patent number: 10497149Abstract: An image processing apparatus according to one embodiment determines target resolutions of a plurality of source images based on a first horizontal direction size and a first vertical direction size which are a horizontal direction size and a vertical direction size of a backlight control unit of a first display, and a second horizontal direction size and a second vertical direction size which are a horizontal direction size and a vertical direction size of a backlight control unit of a second display, and converts the resolution of each of a plurality of source images such that the resolution of each of a plurality of source images becomes the target resolution.Type: GrantFiled: January 3, 2018Date of Patent: December 3, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Ryuichi Igarashi, Seiji Mochizuki, Katsushige Matsubara, Toshiyuki Kaya
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Patent number: 10461956Abstract: A semiconductor device includes a plurality of IP cores, a plurality of storage devices, a configuration information acquiring unit that acquires configuration information for specifying a timing when the IP core accesses the storage device, and an allocation determining unit that determines the storage device allocated to the IP core. The configuration information acquiring unit acquires configuration information regarding a first IP core and configuration information regarding a second IP core. The allocation determining unit determines, based on the configuration information, whether an access timing by the first IP core is the same as an access timing by the second IP core, and when it is determined that the access timings are the same, determines allocation in such a way that the storage device allocated to the first IP core becomes different from the storage device allocated to the second IP core.Type: GrantFiled: June 23, 2017Date of Patent: October 29, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Tetsuji Tsuda, Masaru Hase, Yuki Inoue, Katsushige Matsubara