Patents by Inventor Katsuya Kosaki

Katsuya Kosaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6992016
    Abstract: Air trapped in a blind hole during processing of the blind hole with a liquid is eliminated by circulating the liquid along a surface-to-be-processed in substantially a single direction at all times and by setting a velocity gradient of the liquid over the surface to at least 300/second.
    Type: Grant
    Filed: December 2, 2004
    Date of Patent: January 31, 2006
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takeo Nakamoto, Katsuya Kosaki, Masaru Kinugawa
  • Publication number: 20050092431
    Abstract: Air trapped in a blind hole during processing of the blind hole with a liquid is eliminated by circulating the liquid along a surface-to-be-processed in substantially a single direction at all times and by setting a velocity gradient of the liquid over the surface to at least 300/second.
    Type: Application
    Filed: December 2, 2004
    Publication date: May 5, 2005
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takeo Nakamoto, Katsuya Kosaki, Masaru Kinugawa
  • Patent number: 6849865
    Abstract: An air trap in a blind hole is eliminated by circulating a liquid chemical along a surface-to-be-processed in substantially a given direction at all times and by setting a velocity gradient of the liquid chemical over the surface to 300/second or more thereby eliminating the air trap in the blind hole.
    Type: Grant
    Filed: July 10, 2003
    Date of Patent: February 1, 2005
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takeo Nakamoto, Katsuya Kosaki, Masaru Kinugawa
  • Publication number: 20040060824
    Abstract: By means of a pump for supplying a processing fluid such as a plating fluid to a closed processing cup such as a closed plating cup, at least either the pressure or flow rate of the processing fluid or plating fluid circulating within the closed processing cup or the closed plating cup is cyclically changed. Further, the direction of circulation of the processing fluid circulating within the closed processing cup is also changed cyclically. Under a method of manufacturing a semiconductor device and a method of manufacturing a printed board, a semiconductor wafer and a printed board are disposed in the closed plating cup such that blind holes formed by closing openings on one end of via holes or openings on one end of through holes are brought into contact with a circulating plating fluid, thereby eliminating air bubbles that remain. As a result, a manufacturing yield or performance of a product is improved.
    Type: Application
    Filed: September 16, 2003
    Publication date: April 1, 2004
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Katsuya Kosaki, Takeo Nakamoto
  • Patent number: 6603190
    Abstract: A semiconductor device having a plated heat sink (PHS) layer on the back surface, preventing a short circuit between a bonding wire, and a first metal layer. A method of making a semiconductor device including forming a catalyst layer on a bottom of a first separation groove in the front surface of a semiconductor substrate, and forming the first metal layer selectively in the first separation groove by electroless plating, using the catalyst layer as a catalyst.
    Type: Grant
    Filed: November 8, 2001
    Date of Patent: August 5, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Katsuya Kosaki, Hirofumi Nakano, Tetsuo Kunii
  • Patent number: 6500325
    Abstract: A method of plating which improves the uniformity of a plated coating thickness without changing the flow velocity of a feed plating solution. An aperture at a center of a mesh anode electrode of a plating apparatus produces an electric field density distribution between the mesh anode electrode and a wafer that is lower in the central portion of the wafer than at the edge portion of the wafer.
    Type: Grant
    Filed: December 29, 2000
    Date of Patent: December 31, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Katsuya Kosaki, Masahiro Tamaki
  • Publication number: 20020139684
    Abstract: By means of a pump for supplying a plating fluid to a closed plating cup, at least either the pressure or flow rate of the plating fluid circulating within the closed plating cup is cyclically changed. Alternatively, the direction of circulation of the plating fluid circulating within the closed plating cup maybe also changed cyclically. Under a method of manufacturing a semiconductor device or a method of manufacturing a printed board, a semiconductor wafer or a printed board are disposed in the closed plating cup such that blind holes formed by closing openings on one end of via holes or openings on one end of through holes are brought into contact with a circulating plating fluid, thereby eliminating air bubbles that would remain. As a result, a manufacturing yield or performance of a product is improved.
    Type: Application
    Filed: August 2, 2001
    Publication date: October 3, 2002
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Katsuya Kosaki, Takeo Nakamoto
  • Publication number: 20020139663
    Abstract: By means of a pump for supplying a processing fluid such as a plating fluid to a closed processing cup such as a closed plating cup, at least either the pressure or flow rate of the processing fluid or plating fluid circulating within the closed processing cup or the closed plating cup is cyclically changed. Further, the direction of circulation of the processing fluid circulating within the closed processing cup is also changed cyclically. Under a method of manufacturing a semiconductor device and a method of manufacturing a printed board, a semiconductor wafer and a printed board are disposed in the closed plating cup such that blind holes formed by closing openings on one end of via holes or openings on one end of through holes are brought into contact with a circulating plating fluid, thereby eliminating air bubbles that remain. As a result, a manufacturing yield or performance of a product is improved.
    Type: Application
    Filed: March 11, 2002
    Publication date: October 3, 2002
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Katsuya Kosaki, Takeo Nakamoto
  • Patent number: 6391770
    Abstract: In a semiconductor device, an opening having a high aspect ratio from a back surface of a GaAs substrate and is formed by anisotropic dry etching. After an Au film is deposited on the entire back surface of the GaAs substrate, including inside of the opening, a Ni alloy is non-electrolytically plated. The Ni film can also be deposited on the inner wall and bottom of the opening. An IC substrate or FET may have the Ni film only at an area corresponding to the via hole. The back surface of the IC substrate or FET and the front surface of a package substrate are bonded to each other by AuSn solder poorly wetting the Ni film.
    Type: Grant
    Filed: June 8, 2001
    Date of Patent: May 21, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Katsuya Kosaki, Masahiro Tamaki, Takao Ishida
  • Publication number: 20020048903
    Abstract: A semiconductor device having a PHS layer on the back surface thereof, preventing from a short circuit between a bonding wire and a first metal layer. Forming catalyst layer on a bottom of a first separation groove formed in the front surface of a semiconductor substrate, forming the first metal layer selectively in the first separation groove by an electroless plating technique using the catalyst layer as a catalyst.
    Type: Application
    Filed: November 8, 2001
    Publication date: April 25, 2002
    Inventors: Katsuya Kosaki, Hirofumi Nakano, Tetsuo Kunii
  • Patent number: 6335265
    Abstract: A semiconductor device has a plated heat sink layer on the back surface, preventing a short-circuit between a bonding wire and a first metal layer. A method of making a semiconductor device includes forming a catalyst layer on a bottom of a first separation groove in the front surface of a semiconductor substrate, forming a first metal layer selectively in the first separation groove by electroless plating, using the catalyst layer as a catalyst.
    Type: Grant
    Filed: November 23, 1999
    Date of Patent: January 1, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Katsuya Kosaki, Hirofumi Nakano, Tetsuo Kunii
  • Publication number: 20010028113
    Abstract: In the semiconductor device, an opening 3 having a high aspect ratio is made from the back surface of a GaAs substrate 1 by anisotropic dry etching. After an Au film 4 is deposited on the entire back surface of the Gabs substrate inclusive of the inside of the opening 3, the entire back surface is subjected to Ni alloy non-electrolytic plating so that an Ni film 9a can be also deposited on the inner wall and bottom of the opening 3 can be obtained. An IC substrate or FET with the Ni film 9a left only at the area corresponding to a via hole. The back surface of the IC substrate or FET and the front surface of a package substrate are bonded to each-other by AuSn solder having poor wetting for the Ni film 9a.
    Type: Application
    Filed: June 8, 2001
    Publication date: October 11, 2001
    Inventors: Katsuya Kosaki, Masahiro Tamaki, Takao Ishida
  • Patent number: 6268619
    Abstract: In a semiconductor device, an opening having a high aspect ratio extends from a back surface of a GaAs substrate and is formed by anisotropic dry etching. After an Au film is deposited on the entire back surface of the GaAs substrate, including inside of the opening, a Ni alloy is non-electrolytically plated. The Ni film can also be deposited on the inner wall and the bottom of the opening. An IC substrate or FET may have the Ni film only at an area corresponding to the via hole. The back surface of the IC substrate or FET and the front surface of a package substrate are bonded to each other by AuSn solder poorly wetting the Ni film.
    Type: Grant
    Filed: March 11, 1998
    Date of Patent: July 31, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Katsuya Kosaki, Masahiro Tamaki, Takao Ishida
  • Patent number: 6245596
    Abstract: A method of producing a semiconductor device having a heat dissipating metal layer wherein the number of patterning steps is reduced, laser dicing produces a better profile, and first and second metal layers are prevented from separating from each other, and a semiconductor device produced by the method. The number of patterning steps is reduced by employing a flat exposure step for photoresist with mask alignment. A better appearance is obtained by forming the metal layers which connect the semiconductor devices with each other from a first metal layer having a lower melting point and a second metal layer having a higher melting point and severing the first metal layer and the second metal layer successively, from the first metal layer side. A second metal layer is prevented from peeling by preventing oxidation of the plated feeder layer through plating of the second metal layer.
    Type: Grant
    Filed: October 27, 1999
    Date of Patent: June 12, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Katsuya Kosaki, Masahiro Tamaki, Hiroshi Matsuoka
  • Publication number: 20010000891
    Abstract: The present invention provides a plating apparatus and a method of plating, which improve the uniformity of the plate coat thickness without changing the flow velocity of feeding the plating solution.
    Type: Application
    Filed: December 29, 2000
    Publication date: May 10, 2001
    Inventors: Katsuya Kosaki, Masahiro Tamaki
  • Patent number: 6210554
    Abstract: A method of plating which improves the uniformity of a plated coating thickness without changing the flow velocity of a feed plating solution. An aperture at a center of a mesh anode electrode of a plating apparatus produces an electric field density distribution between the mesh anode electrode and a wafer that is lower in the central portion of the wafer than at the edge portion of the wafer.
    Type: Grant
    Filed: December 21, 1999
    Date of Patent: April 3, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Katsuya Kosaki, Masahiro Tamaki
  • Patent number: 6033540
    Abstract: The present invention provides for a plating apparatus and a method of plating, which improve the uniformity of a plated coating thickness without changing the flow velocity of a feed plating solution. An aperture can be provided at a center of a meshed anode electrode of the plating apparatus to obtain an electric field density distribution between the meshed anode electrode and a wafer that is lower in the central portion of the wafer than in the edge portion of the wafer.
    Type: Grant
    Filed: November 19, 1997
    Date of Patent: March 7, 2000
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Katsuya Kosaki, Masahiro Tamaki
  • Patent number: 6008537
    Abstract: A method of producing a semiconductor device having a heat dissipating metal layer wherein the number of patterning steps is reduced, laser dicing produces a better profile, and first and second matal layers are prevented from separating from each other, and a semiconductor device produced by the method. The number of patterning steps is reduced by employing a flat exposure step for photoresist with mask alignment, A better appearance is obtained by forming the metal layers which connect the semiconductor devices with each other from a first metal layer having a lower melting point and a second metal layer having a higher melting point and severing the first metal layer and the second metal layer successively, from the first metal layer side. A second metal layer is prevented from peeling by preventing oxidation of the plated feeder layer through plating of the second metal layer.
    Type: Grant
    Filed: August 14, 1998
    Date of Patent: December 28, 1999
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Katsuya Kosaki, Masahiro Tamaki, Hiroshi Matsuoka
  • Patent number: 5998238
    Abstract: A method of fabricating a semiconductor device includes forming a first chip separating groove such that its depth is less than the total depth of the wafer, forming a first metallization layer inside the first chip separating groove, thinning the wafer, forming a second chip separating groove in a region opposite the first chip separating groove of the rear surface of the wafer so that the wafer is separated into a plurality of semiconductor chips, forming metallization layer inside the second chip separating groove, forming a PHS layer on the entire rear surface of the wafer, and cutting the wafer at the chip separating groove, thereby producing a semiconductor device. The burr produced when the wafer is cut does not protrude from the rear surface of the wafer, assuring good adhesion between the semiconductor chip and a chip carrier, realizing a semiconductor device of a good heat dispersion characteristic and, therefore, of high reliability.
    Type: Grant
    Filed: June 8, 1998
    Date of Patent: December 7, 1999
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Katsuya Kosaki
  • Patent number: 5872396
    Abstract: A method of fabricating a semiconductor device includes forming a first chip separating in a wafer having a groove depth is less than the thickness of the wafer, forming a first metallization layer inside the first chip separating groove, thinning the wafer, forming a second chip separating groove in a region opposite the first chip separating groove at the rear surface of the wafer for separating the wafer into a plurality of semiconductor chips, forming a metallization layer inside the second chip separating groove, forming a PHS layer on the entire rear surface of the wafer, and cutting the wafer at the chip separating groove, thereby producing a semiconductor device. The burr produced when the wafer is cut does not protrude from the rear surface of the wafer, assuring good adhesion between the semiconductor chip and a chip carrier, realizing a semiconductor device of a good heat dispersion characteristic and, therefore, of high reliability.
    Type: Grant
    Filed: October 25, 1995
    Date of Patent: February 16, 1999
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Katsuya Kosaki