Abstract: A storage device according to embodiments includes a first conductive layer; a second conductive layer; a resistance change element provided between the first conductive layer and the second conductive layer; and an intermediate layer provided in any one of a position between the resistance change element and the first conductive layer and a position between the resistance change element and the second conductive layer, the intermediate layer containing at least one element of silicon (Si) and germanium (Ge), tellurium (Te), and aluminum (Al).

Abstract: A semiconductor storage device is disclosed. The device includes: a first conductive layer; a second conductive layer apart from the first conductive layer in a first direction; a variable resistance layer provided between the first conductive layer and the second conductive layer; a third conductive layer provided between the first conductive layer and the variable resistance layer; a nonlinear layer provided between the first conductive layer and the third conductive layer; and a first insulating layer provided at least between the first conductive layer and the nonlinear layer or between the third conductive layer and the nonlinear layer. The first insulating layer includes nitrogen (N) and boron (B).

Abstract: A semiconductor device may include, but is not limited to, first and second memory regions, and first to fifth control circuits. The first and second memory regions are mutually exclusive at the same time. The first control circuit performs a first access to the first memory region. The second control circuit performs a second access to the second memory region. The third control circuit controls activation and deactivation of the first and second control circuits based on a first logic received from a plurality of first external terminals. The fourth control circuit switches between the first and second accesses based on at least a second logic received from a second external terminal. The fifth control circuit controls validation and invalidation of the fourth control circuit.

Abstract: A semiconductor device may include, but is not limited to, first and second memory regions, and first to fifth control circuits. The first and second memory regions are mutually exclusive at the same time. The first control circuit performs a first access to the first memory region. The second control circuit performs a second access to the second memory region. The third control circuit controls activation and deactivation of the first and second control circuits based on a first logic received from a plurality of first external terminals. The fourth control circuit switches between the first and second accesses based on at least a second logic received from a second external terminal. The fifth control circuit controls validation and invalidation of the fourth control circuit.