Patents by Inventor Katsuyoshi Matsuura
Katsuyoshi Matsuura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10651272Abstract: One aspect of a semiconductor device includes a plurality of first structures, in which each of the first structures includes: a first N-type region; a P-type region which is surrounded by the first N-type region; and a second N-type region which is surrounded by the P-type region. The first N-type region and the P-type region are wired, and the plurality of first structures are connected in parallel to form one diode.Type: GrantFiled: February 22, 2018Date of Patent: May 12, 2020Assignee: UNITED SEMICONDUCTOR JAPAN CO., LTD.Inventor: Katsuyoshi Matsuura
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Patent number: 10236286Abstract: A semiconductor integrated circuit apparatus and a manufacturing method for the same are provided in such a manner that a leak current caused by a ballast resistor is reduced, and at the same time, the inconsistency in the leak current is reduced. The peak impurity concentration of the ballast resistors is made smaller than the peak impurity concentration in the extension regions, and the depth of the ballast resistors is made greater than the depth of the extension regions.Type: GrantFiled: May 15, 2017Date of Patent: March 19, 2019Assignee: MIE FUJITSU SEMICONDUCTOR LIMITEDInventors: Katsuyoshi Matsuura, Junichi Ariyoshi
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Publication number: 20180269286Abstract: One aspect of a semiconductor device includes a plurality of first structures, in which each of the first structures includes: a first N-type region; a P-type region which is surrounded by the first N-type region; and a second N-type region which is surrounded by the P-type region. The first N-type region and the P-type region are wired, and the plurality of first structures are connected in parallel to form one diode.Type: ApplicationFiled: February 22, 2018Publication date: September 20, 2018Applicant: MIE FUJITSU SEMICONDUCTOR LIMITEDInventor: Katsuyoshi Matsuura
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Patent number: 9935097Abstract: A semiconductor integrated circuit apparatus and a manufacturing method for the same are provided in such a manner that a leak current caused by a ballast resistor is reduced, and at the same time, the inconsistency in the leak current is reduced. The peak impurity concentration of the ballast resistors is made smaller than the peak impurity concentration in the extension regions, and the depth of the ballast resistors is made greater than the depth of the extension regions.Type: GrantFiled: January 12, 2015Date of Patent: April 3, 2018Assignee: MIE FUJITSU SEMICONDUCTOR LIMITEDInventors: Katsuyoshi Matsuura, Junichi Ariyoshi
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Publication number: 20170250177Abstract: A semiconductor integrated circuit apparatus and a manufacturing method for the same are provided in such a manner that a leak current caused by a ballast resistor is reduced, and at the same time, the inconsistency in the leak current is reduced. The peak impurity concentration of the ballast resistors is made smaller than the peak impurity concentration in the extension regions, and the depth of the ballast resistors is made greater than the depth of the extension regions.Type: ApplicationFiled: May 15, 2017Publication date: August 31, 2017Applicant: MIE FUJITSU SEMICONDUCTOR LIMITEDInventors: Katsuyoshi Matsuura, Junichi Ariyoshi
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Patent number: 9093418Abstract: A ferroelectric capacitor is formed on a semiconductor substrate, the ferroelectric capacitor comprising a lower electrode, a ferroelectric film and an upper electrode stacked in an order recited. A first capacitor protective film of aluminum oxide having a thickness equal to or thicker than 30 nm is formed covering the ferroelectric capacitor. A first insulating film of silicon oxide is formed on the first capacitor protective film by chemical vapor deposition using high density plasma.Type: GrantFiled: January 17, 2014Date of Patent: July 28, 2015Assignee: FUJITSU SEMICONDUCTOR LIMITEDInventor: Katsuyoshi Matsuura
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Publication number: 20150200191Abstract: A semiconductor integrated circuit apparatus and a manufacturing method for the same are provided in such a manner that a leak current caused by a ballast resistor is reduced, and at the same time, the inconsistency in the leak current is reduced. The peak impurity concentration of the ballast resistors is made smaller than the peak impurity concentration in the extension regions, and the depth of the ballast resistors is made greater than the depth of the extension regions.Type: ApplicationFiled: January 12, 2015Publication date: July 16, 2015Inventors: Katsuyoshi Matsuura, Junichi Ariyoshi
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Patent number: 8785274Abstract: A method for manufacturing a semiconductor device includes preparing a semiconductor substrate having a first region of a first electrical conduction type as a part of a surface layer of the semiconductor substrate and a first gate electrode and a capacitor structure, the first gate electrode and the capacitor structure being disposed on the first region; forming a first insulating film covering the first gate electrode and the capacitor structure, the first insulating film being covering the surface of the semiconductor substrate; implanting a first impurity of a second electrical conduction type into the semiconductor substrate, so as to form a region of the second electrical conduction type in each of a second region and a third region, the second region being a region between the first gate electrode and the capacitor structure, the third region being a region opposite to the capacitor structure with the first gate electrode therebetween.Type: GrantFiled: May 24, 2010Date of Patent: July 22, 2014Assignee: Fujitsu Semiconductor LimitedInventors: Katsuyoshi Matsuura, Masayoshi Asano, Hiroyuki Ogawa, Myounggoo Lee
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Publication number: 20140134754Abstract: A ferroelectric capacitor is formed on a semiconductor substrate, the ferroelectric capacitor comprising a lower electrode, a ferroelectric film and an upper electrode stacked in an order recited. A first capacitor protective film of aluminum oxide having a thickness equal to or thicker than 30 nm is formed covering the ferroelectric capacitor. A first insulating film of silicon oxide is formed on the first capacitor protective film by chemical vapor deposition using high density plasma.Type: ApplicationFiled: January 17, 2014Publication date: May 15, 2014Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: Katsuyoshi Matsuura
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Patent number: 7893472Abstract: A ferroelectric memory device manufacturing method includes the steps of forming an interlayer isolating film for covering a transistor formed on a semiconductor substrate; forming a conductive plug in the interlayer insulating film to contact a diffusion region of the transistor formed on the semiconductor substrate; forming a ferroelectric capacitor including a lower electrode, a ferroelectric film and an upper electrode; and forming a compound film including silicon (Si) and a CH group on a surface of the interlayer insulating film and a surface of the conductive plug by depositing a Si compound containing Si atoms and the CH groups; wherein the compound film is formed after forming the conductive plug, and the compound film is formed before forming the lower electrode; and a self-orientation film is formed on a surface of the compound film.Type: GrantFiled: July 22, 2008Date of Patent: February 22, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Naoya Sashida, Katsuyoshi Matsuura
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Publication number: 20100304539Abstract: A method for manufacturing a semiconductor device includes preparing a semiconductor substrate having a first region of a first electrical conduction type as a part of a surface layer of the semiconductor substrate and a first gate electrode and a capacitor structure, the first gate electrode and the capacitor structure being disposed on the first region; forming a first insulating film covering the first gate electrode and the capacitor structure, the first insulating film being covering the surface of the semiconductor substrate; implanting a first impurity of a second electrical conduction type into the semiconductor substrate, so as to form a region of the second electrical conduction type in each of a second region and a third region, the second region being a region between the first gate electrode and the capacitor structure, the third region being a region opposite to the capacitor structure with the first gate electrode therebetween.Type: ApplicationFiled: May 24, 2010Publication date: December 2, 2010Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Katsuyoshi Matsuura, Masayoshi Asano, Hiroyuki Ogawa, Myounggoo Lee
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Publication number: 20100068829Abstract: A ferroelectric capacitor is formed on a semiconductor substrate, the ferroelectric capacitor comprising a lower electrode, a ferroelectric film and an upper electrode stacked in an order recited. A first capacitor protective film of aluminum oxide having a thickness equal to or thicker than 30 nm is formed covering the ferroelectric capacitor. A first insulating film of silicon oxide is formed on the first capacitor protective film by chemical vapor deposition using high density plasma.Type: ApplicationFiled: November 23, 2009Publication date: March 18, 2010Applicant: FUJITSU MICROELECTRONICS LIMITEDInventor: Katsuyoshi Matsuura
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Patent number: 7622346Abstract: A ferroelectric capacitor formation method necessary for stably fabricating an FeRAM and a semiconductor device fabrication method. After a PZT film is deposited on a lower electrode layer, the PZT film is crystallized by performing heat treatment in an atmosphere of a mixed gas which contains O2 gas and Ar gas. In this case, the flow rate of the O2 gas is controlled by one mass flow controller. The flow rate of the Ar gas used for purging and the flow rate of the Ar gas used for adjusting O2 gas concentration are controlled by different mass flow controllers. Before raising the temperature, the O2 gas, the Ar gas used for purging, and the Ar gas used for adjusting O2 gas concentration are made to flow at predetermined flow rates. Only the Ar gas used for purging is stopped, raising the temperature is begun, and the heat treatment is performed. At this time the O2 gas and the Ar gas used for adjusting O2 gas concentration flow at the predetermined flow rates.Type: GrantFiled: June 20, 2006Date of Patent: November 24, 2009Assignee: Fujitsu Microelectronics LimitedInventors: Mitsushi Fujiki, Katsuyoshi Matsuura, Genichi Komuro
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Patent number: 7616171Abstract: The present invention discloses a connecting part of conductor pattern, which is connected to a conductor pattern formed on a surface of an insulating substrate and which has at least one dent on the surface, and a conductor patterns-connected structure obtained by electrically connecting the connecting parts of conductor patterns, mentioned above, to each other with a conductive material which fills the inside of the dent of each connecting part and further is adhered to each connecting part.Type: GrantFiled: September 19, 2007Date of Patent: November 10, 2009Assignee: Lintec CorporationInventors: Taiga Matsushita, Katumi Katakura, Katsuyoshi Matsuura
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Patent number: 7601585Abstract: In pattern-forming ferroelectric capacitor structures by a one mask etching, after an Ir film to be a lower electrode film is formed, an AlOx film to be an oxide reduction film reducing an Ir oxide which is formed on a surface layer of the lower electric film is deposited on the lower electrode film, and then this oxide reduction film is removed by, for example, a dilute hydrofluoric acid treatment.Type: GrantFiled: October 27, 2006Date of Patent: October 13, 2009Assignee: Fujitsu Microelectronics LimitedInventor: Katsuyoshi Matsuura
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Patent number: 7550302Abstract: The present invention provides a method of manufacturing a semiconductor device. The method includes the steps of forming a first interlayer insulating film over a silicon substrate; forming a first conductive film on the first interlayer insulating film; forming a first ferroelectric film, which is crystallized, on the first conductive film; annealing the first ferroelectric film; after the annealing, forming, on the first ferroelectric film, a second ferroelectric film made of an amorphous material or a microcrystalline material; forming a second conductive film on the second ferroelectric film; and forming a capacitor by patterning the first and second conductive films and the first and second ferroelectric films.Type: GrantFiled: October 30, 2006Date of Patent: June 23, 2009Assignee: Fujitsu Microelectronics LimitedInventors: Wensheng Wang, Masaaki Nakabayashi, Katsuyoshi Matsuura
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Patent number: 7501325Abstract: The method for fabricating the semiconductor device comprises: the step of forming a ferroelectric capacitor over a semiconductor substrate 10; the step of forming an insulating film 54, covering the ferroelectric capacitor; the step of processing thermal treatment to eliminate hydrogen and/or water adsorbed on a surface of the insulating film 54 or occluded in the insulating film 54; and the step of forming a capacitor protective film 56 of an aluminum oxide film over the insulating film 54. The step of processing the thermal treatment and the step of forming the capacitor protective film are performed continuously in the same system without exposing to an ambient atmosphere.Type: GrantFiled: June 27, 2005Date of Patent: March 10, 2009Assignee: Fujitsu Microelectronics LimitedInventors: Katsuyoshi Matsuura, Naoya Sashida
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Patent number: 7498947Abstract: An antenna circuit includes a plurality of antenna circuit units on a circuit substrate. The plurality of antenna circuit units includes: a large antenna circuit unit whose circuit size is large; and a small antenna circuit unit whose circuit size is smaller than the size of the large antenna circuit unit, the small antenna circuit unit provided inside the large antenna circuit unit and provided detachable from the large antenna circuit unit.Type: GrantFiled: December 19, 2006Date of Patent: March 3, 2009Assignee: Lintec CorporationInventors: Katsuyoshi Matsuura, Katsumi Katakura, Taiga Matsushita
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Patent number: 7459361Abstract: A semiconductor device fabrication method includes the steps of forming a conductive plug in an insulating layer on a semiconductor substrate so as to be connected to an element on the substrate; forming a titanium aluminum nitride (TiAlN) oxygen barrier film over the conductive plug; forming a titanium (Ti) film over the oxygen barrier film; applying a thermal process to the titanium film in nitrogen atmosphere to allow the titanium film to turn into a titanium nitride (TiN) film; and forming a lower electrode film of a capacitor over the titanium nitride film.Type: GrantFiled: February 22, 2006Date of Patent: December 2, 2008Assignee: Fujitsu LimitedInventor: Katsuyoshi Matsuura
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Publication number: 20080277706Abstract: A ferroelectric memory device manufacturing method includes the steps of forming an interlayer isolating film for covering a transistor formed on a semiconductor substrate; forming a conductive plug in the interlayer insulating film to contact a diffusion region of the transistor formed on the semiconductor substrate; forming a ferroelectric capacitor including a lower electrode, a ferroelectric film and an upper electrode; and forming a compound film including silicon (Si) and a CH group on a surface of the interlayer insulating film and a surface of the conductive plug by depositing a Si compound containing Si atoms and the CH groups; wherein the compound film is formed after forming the conductive plug, and the compound film is formed before forming the lower electrode; and a self-orientation film is formed on a surface of the compound film.Type: ApplicationFiled: July 22, 2008Publication date: November 13, 2008Applicant: FUJITSU LIMITEDInventors: Naoya SASHIDA, Katsuyoshi MATSUURA